A 12 bit 200 MHz low glitch CMOS D/A converter. - Anne Van den Bosch; Marc Borremans; Jan Vandenbussche; Geert Van der Plas; Augusto Manuel Marques; José Bastos; Michiel Steyaert; Georges G. E. Gielen; Willy Sansen (CICC, 1998)

A current steering architecture for 12-bit high-speed D/A converters. - Augusto Manuel Marques; José Bastos; Michiel Steyaert; Willy Sansen (ICECS, 1998)

Settling time analysis of third order systems. - Augusto Manuel Marques; Yves Geerts; Michiel Steyaert; Willy Sansen (ICECS, 1998)

Analysis of the trade-off between bandwidth, resolution, and power in ΔΣ analog to digital converters. - Augusto Manuel Marques; Valentino Peluso; Michiel Steyaert; Willy M. C. Sansen (ICECS, 1998)

A 12-bit intrinsic accuracy high-speed CMOS DAC. - José Bastos; Augusto Manuel Marques; Michel S. J. Steyaert; Willy Sansen (IEEE J. Solid State Circuits, 1998)

A 15-b resolution 2-MHz Nyquist rate ΔΣ ADC in a 1-μm CMOS technology. - Augusto Manuel Marques; Vincenzo Peluso; Michel S. J. Steyaert; Willy Sansen (IEEE J. Solid State Circuits, 1998)

A 900-mV low-power ΔΣ A/D converter with 77-dB dynamic range. - Vincenzo Peluso; Peter J. Vancorenland; Augusto Manuel Marques; Michel S. J. Steyaert; Willy Sansen (IEEE J. Solid State Circuits, 1998)

Theory of PLL fractional-N frequency synthesizers. - Augusto Manuel Marques; Michiel S. J. Steyaert; Willy M. C. Sansen (Wirel. Networks, 1998)

A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications. - Yves Geerts; Augusto Manuel Marques; Michel S. J. Steyaert; Willy Sansen (IEEE J. Solid State Circuits, 1999)