A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction. - Koen Uyttenhove; Augusto Marques; Margot Steyaert (CICC, 2000)

A 1.22/6.7 ppm/°C VCO with frequency-drifting compensator in 60 nm CMOS. - Lan-Chou Cho; Hsiang-Hui Chang; Augusto Marques; Albert Yang; Chinq-Shiun Chiu; Guang-Kaai Dehng (A-SSCC, 2011)

A 65-nm GSM/GPRS/EDGE SoC With Integrated BT/FM. - Tzung-Han Wu; Hsiang-Hui Chang; Shin-Fu Chen; Chinq-Shiun Chiu; Li-Shin Lai; Chi-Hsueh Wang; Song-Yu Yang; Ta-Hsin Lin; Jhy-Rong Chen; Hung-Chieh Tsai; Chi-Yao Yu; Sheng-Yuan Su; et al. (IEEE J. Solid State Circuits, 2013)