HTR: On-Chip Hardware Task Relocation for Partially Reconfigurable FPGAs. - Aurelio Morales-Villanueva; Ann Gordon-Ross (ARC, 2013)

On-chip Context Save and Restore of Hardware Tasks on Partially Reconfigurable FPGAs. - Aurelio Morales-Villanueva; Ann Gordon-Ross (FCCM, 2013)

Partial Region and Bitstream Cost Models for Hardware Multitasking on Partially Reconfigurable FPGAs. - Aurelio Morales-Villanueva; Ann Gordon-Ross (IPDPS Workshops, 2015)

Configuration prefetching and reuse for preemptive hardware multitasking on partially reconfigurable FPGAs. - Aurelio Morales-Villanueva; Rohit Kumar; Ann Gordon-Ross (DATE, 2016)

Uncertainty Evaluation of a Gas Turbine Model Based on a Nonlinear Autoregressive Exogenous Model and Monte Carlo Dropout. - Armando Cajahuaringa; Rubén Aquize Palacios; Juan Moises Maurício Villanueva; Aurelio Morales-Villanueva; José A. D. Machuca; Juan Contreras; Kiara Rodríguez Bautista (Sensors, 2024)