XPRESS: A Cell Layout Generator with Integrated Transistor Folding. - Avaneendra Gupta; Siang-Chun The; John P. Hayes (ED&TC, 1996)

Width minimization of two-dimensional CMOS cells using integer programming. - Avaneendra Gupta; John P. Hayes (ICCAD, 1996)

CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells. - Avaneendra Gupta; John P. Hayes (DAC, 1997)

A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells. - Avaneendra Gupta; John P. Hayes (VLSI Design, 1997)

Integer-programming-based layout synthesis of two-dimensional CMOS cells. - Avaneendra Gupta (1997)

Optimal 2-D cell layout with integrated transistor folding. - Avaneendra Gupta; John P. Hayes (ICCAD, 1998)

Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells. - Avaneendra Gupta; John P. Hayes (VLSI Design, 1999)

CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells. - Avaneendra Gupta; John P. Hayes (ACM Trans. Design Autom. Electr. Syst., 2000)