Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays. - Avik Chakraborty (VLSI Design, 2005)

Testability of AND-EXOR Based Iterative Logic Arrays - Avik Chakraborty (CoRR, 2008)

Testing of Bridging Faults in AND-EXOR based Reversible Logic Circuits - Avik Chakraborty (CoRR, 2010)

Counting Cycles in Reversible Cellular Automata. - Sukanta Das; Avik Chakraborty; Biplab K. Sikdar (ACRI, 2012)

Analysis of Reachability Tree for Identification of Cyclic and Acyclic CA States. - Nazma Naskar; Avik Chakraborty; Pradipta Maji; Sukanta Das (ACRI, 2012)

A Framework to Counter Statistical Ineffective Fault Analysis of Block Ciphers Using Domain Transformation and Error Correction. - Sayandeep Saha; Dirmanto Jap; Debapriya Basu Roy; Avik Chakraborty; Shivam Bhasin; Debdeep Mukhopadhyay (IEEE Trans. Inf. Forensics Secur., 2020)