Power management architecture of the 2nd generation Intel® Core microarchitecture, formerly codenamed Sandy Bridge. - Efi Rotem; Alon Naveh; Doron Rajwan; Avinash Ananthakrishnan; Eliezer Weissmann (Hot Chips Symposium, 2011)

Power-Management Architecture of the Intel Microarchitecture Code-Named Sandy Bridge. - Efraim Rotem; Alon Naveh; Avinash Ananthakrishnan; Eliezer Weissmann; Doron Rajwan (IEEE Micro, 2012)

Power management on 14 nm Intel® Core- M processor. - Anant Deval; Avinash Ananthakrishnan; Craig Forbell (COOL Chips, 2015)