Avinash Karanth
Orcid: 0000-0002-9472-4637Affiliations:
- Ohio University
According to our database1,
Avinash Karanth
authored at least 108 papers
between 2004 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
A High-Performance and Energy-Efficient Photonic Architecture for Multi-DNN Acceleration.
IEEE Trans. Parallel Distributed Syst., January, 2024
IEEE Trans. Computers, January, 2024
2023
Reclaimer: A Reinforcement Learning Approach to Dynamic Resource Allocation for Cloud Microservices.
CoRR, 2023
Proceedings of the 54th ACM Technical Symposium on Computer Science Education, Volume 1, 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023
2022
SPRINT: A High-Performance, Energy-Efficient, and Scalable Chiplet-Based Accelerator With Photonic Interconnects for CNN Inference.
IEEE Trans. Parallel Distributed Syst., 2022
IEEE Trans. Emerg. Top. Comput., 2022
Exploiting Wireless Technology for Energy-Efficient Accelerators With Multiple Dataflows and Precision.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With Photonic Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Proceedings of the SIGCSE 2022: The 53rd ACM Technical Symposium on Computer Science Education, 2022
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
2021
Albireo: Energy-Efficient Acceleration of Convolutional Neural Networks via Silicon Photonics.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
GCNAX: A Flexible and Energy-efficient Accelerator for Graph Convolutional Neural Networks.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
CSCNN: Algorithm-hardware Co-design for CNN Accelerators using Centrosymmetric Filters.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
Dynamic Voltage and Frequency Scaling to Improve Energy-Efficiency of Hardware Accelerators.
Proceedings of the 28th IEEE International Conference on High Performance Computing, 2021
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Scaling Deep-Learning Inference with Chiplet-based Architecture and Photonic Interconnects.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
Hardware-Level Thread Migration to Reduce On-Chip Data Movement Via Reinforcement Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Guest Editors' Introduction to the Special Issue on Machine Learning Architectures and Accelerators.
IEEE Trans. Computers, 2020
Reconfigurable Gates with Sub-10nm Ambipolar SB-FinFETs for Logic Locking & Obfuscation.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
DozzNoC: Reducing Static and Dynamic Energy in NoCs with Low-latency Voltage Regulators using Machine Learning.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
2019
Sustainability in Network-on-Chips by Exploring Heterogeneity in Emerging Technologies.
IEEE Trans. Sustain. Comput., 2019
ACM J. Emerg. Technol. Comput. Syst., 2019
Dynamic Voltage and Frequency Scaling in NoCs With Supervised and Reinforcement Learning Techniques.
Computer, 2019
IntelliNoC: a holistic design framework for energy-efficient and reliable on-chip communication for manycores.
Proceedings of the 46th International Symposium on Computer Architecture, 2019
High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learnin.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
GARUDA: Designing Energy-Efficient Hardware Monitors From High-Level Policies for Secure Information Flow.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
J. Parallel Distributed Comput., 2018
SHARP: Shared Heterogeneous Architecture with Reconfigurable Photonic Network-on-Chip.
ACM J. Emerg. Technol. Comput. Syst., 2018
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Wirel. Pers. Commun., 2017
J. Parallel Distributed Comput., 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Reconfigurable Optical and Wireless (R-OWN) Network-on-Chip for High Performance Computing.
Proceedings of the 3rd ACM International Conference on Nanoscale Computing and Communication, 2016
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016
Proceedings of the 24th IEEE Annual Symposium on High-Performance Interconnects, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
IEEE Trans. Parallel Distributed Syst., 2015
A New Frontier in Ultralow Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures.
IEEE Trans. Computers, 2015
Bandwidth Adaptive Nanophotonic Crossbars with Clockwise/Counter-clockwise Optical Routing.
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the Second Annual International Conference on Nanoscale Computing and Communication, 2015
Proceedings of the 23rd IEEE Annual Symposium on High-Performance Interconnects, 2015
Power and performance analysis of scalable photonic networks for exascale architecture.
Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015
Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
2014
Extending the Performance and Energy-Efficiency of Shared Memory Multicores with Nanophotonic Technology.
IEEE Trans. Parallel Distributed Syst., 2014
Three-Dimensional Stacked Nanophotonic Network-on-Chip Architecture with Minimal Reconfiguration.
IEEE Trans. Computers, 2014
ACM J. Emerg. Technol. Comput. Syst., 2014
QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
2013
Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Evaluating the scalability and performance of 3D stacked reconfigurable nanophotonic interconnects.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Design of a Concentrated Torus Topology with Channel Buffers and Efficient Crossbars in NoCs.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
Energy-efficient Runtime Adaptive Scrubbing in fault-tolerant Network-on-Chips (NoCs) architectures.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
2012
IEEE Wirel. Commun., 2012
JOCN, 2012
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
Energy-Efficient and Fault-Tolerant Unified Buffer and Bufferless Crossbar Architecture for NoCs.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the 2012 International Green Computing Conference, 2012
2011
Design of a performance enhanced and power reduced dual-crossbar Network-on-Chip (NoC) architecture.
Microprocess. Microsystems, 2011
Introduction to the special issue on Networks-on-Chip (NoC) of the Journal of Parallel and Distributed Computing (JPDC).
J. Parallel Distributed Comput., 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture.
Proceedings of the IEEE 19th Annual Symposium on High Performance Interconnects, 2011
2010
Power-Efficient and High-Performance Multi-level Hybrid Nanophotonic Interconnect for Multicores.
Proceedings of the NOCS 2010, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs).
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009
2008
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis.
IEEE Trans. Computers, 2008
IEEE Micro, 2008
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008
2007
Performance adaptive power-aware reconfigurable optical interconnects for high-performance computing (HPC) systems.
Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, 2007
Power-Aware Bandwidth-Reconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Implementation of Dynamic Bandwidth Re-allocation in Optical Interconnects using Microring Resonators.
Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects, 2007
Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture.
Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2007
2006
RAPID: Reconfigurable All-Photonic Interconnect for Parallel and Distributed Computers.
PhD thesis, 2006
A New Dynamic Bandwidth Re-Allocation Technique in Optically Interconnected High-Performance Computing Systems.
Proceedings of the 14th IEEE Symposium on High-Performance Interconnects, 2006
2005
Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors.
IEEE Micro, 2005
2004
An Optical Interconnection Network and a Modified Snooping Protocol for the Design of Large-Scale Symmetric Multiprocessors (SMPs).
IEEE Trans. Parallel Distributed Syst., 2004
A Scalable Architecture for Distributed Shared Memory Multiprocessors Using Optical Interconnects.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004