Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach. - Awais Sani; Philippe Coussy; Cyrille Chavet; Eric Martin 001 (ICECS, 2010)

A methodology based on Transportation problem modeling for designing parallel interleaver architectures. - Awais Sani; Philippe Coussy; Cyrille Chavet; Eric Martin 001 (ICASSP, 2011)

Design and analysis of fuzzy logic based robust PID controller for PWM-based switching converter. - Ghulam Abbas 001; Nacer Abouchi; Awais Sani; Cyril Condemine (ISCAS, 2011)

An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture. - Awais Sani; Philippe Coussy; Cyrille Chavet; Eric Martin 001 (ISCAS, 2011)

A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders. - Oscar Sanchez; Michel Jézéquel; Saeed-ur Rehman; Awais Sani; Cyrille Chavet; Philippe Coussy; Christophe Jégo (SiPS, 2012)

On-chip implementation of memory mapping algorithm to support flexible decoder architecture. - Saeed-ur Rehman; Awais Sani; Philippe Coussy; Cyrille Chavet (ICASSP, 2013)

A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm. - Awais Hussain Sani; Philippe Coussy; Cyrille Chavet (IEEE Trans. Signal Process., 2013)

Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures. - Saeed-ur Rehman; Awais Sani; Cyrille Chavet; Philippe Coussy (ICASSP, 2014)

In-place memory mapping approach for optimized parallel hardware interleaver architectures. - Saeed Ur Reehman; Cyrille Chavet; Philippe Coussy; Awais Sani (DATE, 2015)

A dynamically reconfigurable ECC decoder architecture. - Awais Sani; Philippe Coussy; Cyrille Chavet (DATE, 2016)

Energy proportional computing with OpenCL on a FPGA-based overlay architecture. - Awais Hussain Sani; José Luis Núñez-Yáñez (NORCAS, 2016)