7.5 Gb/s monolithically integrated clock recovery circuit using PLL and 0.3-μm gate length quantum well HEMT's. - Zhi-Gong Wang; Manfred Berroth; Ulrich Nowotny; Peter Hofmann; Axel Hiilsmann; Klaus Köhler; Brian Raynor; Joachim Schneider (IEEE J. Solid State Circuits, 1994)