Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits. - Aymane Bouzafour; Marc Renaudin; Hubert Garavel; Radu Mateescu 001; Wendelin Serwe (ASYNC, 2018)

A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI. - Marc Renaudin; Aymane Bouzafour; Sylvain Engels; Robin Wilson (J. Low Power Electron., 2018)

Modeling an Asynchronous Circuit Dedicated to the Protection Against Physical Attacks. - Radu Mateescu 001; Wendelin Serwe; Aymane Bouzafour; Marc Renaudin (MARS@ETAPS, 2020)