Advanced test methodology for complex SoCs. - Pavan Kumar Datla Jagannadha; Mahmut Yilmaz; Milind Sonawane; Sailendra Chadalavada; Shantanu Sarangi; Bonita Bhaskaran; Ayub Abdollahian (ITC, 2016)

Test method and scheme for low-power validation in modern SOC integrated circuits. - Bonita Bhaskaran; Amit Sanghani; Kaushik Narayanun; Ayub Abdollahian; Amit Laknaur (VTS, 2016)

A programmable method for low-power scan shift in SoC integrated circuits. - Ran Wang 002; Bonita Bhaskaran; Karthikeyan Natarajan; Ayub Abdollahian; Kaushik Narayanun; Krishnendu Chakrabarty; Amit Sanghani (VTS, 2016)

At-speed capture global noise reduction & low-power memory test architecture. - Bonita Bhaskaran; Sailendra Chadalavada; Shantanu Sarangi; Nithin Valentine; Venkat Abilash Reddy Nerallapally; Ayub Abdollahian (VTS, 2017)

An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test. - Seyed Nima Mozaffari; Bonita Bhaskaran; Kaushik Narayanun; Ayub Abdollahian; Vinod Pagalone; Shantanu Sarangi; Jonathon E. Colburn (ITC, 2019)

A Novel Graph-Coloring-Based Solution for Low-Power Scan Shift. - Saurabh Gupta 005; Bonita Bhaskaran; Shantanu Sarangi; Ayub Abdollahian; Jennifer Dworak (IEEE Des. Test, 2020)