Chip-level and Input/Output Interconnects for Gigascale SOCs: Limits and Opportunities. - Azad Naeemi; Muhannad S. Bakir (SoCC, 2006)

Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots. - Gang Huang; Deepak C. Sekar; Azad Naeemi; Kaveh Shakeri; James D. Meindl (CICC, 2007)

Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects. - Azad Naeemi; Reza Sarvari; James D. Meindl (DAC, 2007)

IntSim: A CAD tool for optimization of multilevel interconnect networks. - Deepak C. Sekar; Azad Naeemi; Reza Sarvari; Jeffrey A. Davis; James D. Meindl (ICCAD, 2007)

Carbon nanotube interconnects. - Azad Naeemi; James D. Meindl (ISPD, 2007)

3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation. - Muhannad S. Bakir; Calvin King; Deepak C. Sekar; Hiren D. Thacker; Bing Dang; Gang Huang; Azad Naeemi; James D. Meindl (CICC, 2008)

Physical models for electron transport in graphene nanoribbons and their junctions. - Azad Naeemi; James D. Meindl (ICCAD, 2008)

Nanoelectronics in retrospect, prospect and principle. - James D. Meindl; Azad Naeemi; Muhannad S. Bakir; R. Murali (ISSCC, 2010)

Power Aware Post-manufacture Tuning of Analog Nanocircuits. - Aritra Banerjee; Subho Chatterjee; Azad Naeemi; Abhijit Chatterjee (ETS, 2011)

Interconnection aspects of spin torque devices: Delay, energy-per-bit, and circuit size modeling. - Shaloo Rakheja; Azad Naeemi (ISQED, 2011)

System-level design and performance modeling for multilevel interconnect networks for carbon nanotube field-effect transistors. - Ahmet Ceyhan; Azad Naeemi (ICICDT, 2012)

System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model. - Chenyun Pan; Azad Naeemi (ICICDT, 2012)

Device- and system-level performance modeling for graphene P-N junction logic. - Chenyun Pan; Azad Naeemi (ISQED, 2012)

Interconnect analysis in spin-torque devices: Performance modeling, sptimal repeater insertion, and circuit-size limits. - Shaloo Rakheja; Azad Naeemi (ISQED, 2012)

Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices. - Ahmet Ceyhan; Azad Naeemi (ISQED, 2013)

System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs. - Chenyun Pan; Ahmet Ceyhan; Azad Naeemi (ISQED, 2013)

Performance modeling for interconnects for conventional and emerging switches. - Shaloo Rakheja; Vachan Kumar; Azad Naeemi (SLIP, 2013)

Evaluation of the Potential Performance of Graphene Nanoribbons as On-Chip Interconnects. - Shaloo Rakheja; Vachan Kumar; Azad Naeemi (Proc. IEEE, 2013)

BEOL Scaling Limits and Next Generation Technology Prospects. - Azad Naeemi; Ahmet Ceyhan; Vachan Kumar; Chenyun Pan; Rouhollah M. Iraei; Shaloo Rakheja (DAC, 2014)

Interactive visualizations for teaching quantum mechanics and semiconductor physics. - Rose Peng; Bill Dorn; Azad Naeemi; Nassim Jafarinaimi (FIE, 2014)

Performance modeling for emerging interconnect technologies in CMOS and beyond-CMOS circuits. - Sou-Chi Chang; Ahmet Ceyhan; Vachan Kumar; Azad Naeemi (ISLPED, 2014)

An analytical approach to system-level variation analysis and optimization for multi-core processor. - Chenyun Pan; Saibal Mukhopadhyay; Azad Naeemi (ISQED, 2014)

Pipeline design in spintronic circuits. - Nickvash Kani; Azad Naeemi (NANOARCH, 2014)

Wiring resource minimization for physically-complex Network-on-Chip architectures. - Nickvash Kani; Azad Naeemi (SoCC, 2014)

Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node. - Chenyun Pan; Praveen Raghavan; Francky Catthoor; Zsolt Tokei; Azad Naeemi (ISQED, 2015)

Smart Detector Cell: A Scalable All-Spin Circuit for Low Power Non-Boolean Pattern Recognition. - Hamidreza Aghasi; Ruohollah Mousavi Iraei; Azad Naeemi; Ehsan Afshari (CoRR, 2015)

A Fast System-Level Design Methodology for Heterogeneous Multi-Core Processors Using Emerging Technologies. - Chenyun Pan; Azad Naeemi (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

Device/system performance modeling of stacked lateral NWFET logic. - Victor Huang; Chenyun Pan; Dmitry Yakimets; Praveen Raghavan; Azad Naeemi (ISQED, 2016)

Performance modeling and optimization for on-chip interconnects in 3D memory arrays. - Javaneh Mohseni; Chenyun Pan; Azad Naeemi (ISQED, 2016)

Impact of interconnect variability on circuit performance in advanced technology nodes. - Divya Prasad; Chenyun Pan; Azad Naeemi (ISQED, 2016)

Low-power Spin Valve Logic using Spin-transfer Torque with Automotion of Domain Walls. - Sou-Chi Chang; Sasikanth Manipatruni; Dmitri E. Nikonov; Ian A. Young; Azad Naeemi (CoRR, 2016)

A Proposal for Energy-Efficient Cellular Neural Network based on Spintronic Devices. - Chenyun Pan; Azad Naeemi (CoRR, 2016)

Non-volatile spin wave majority gate at the nanoscale. - Odysseas Zografos; Sourav Dutta; Mauricio Manfrini; Adrien Vaysset; Bart Sorée; Azad Naeemi; Praveen Raghavan; Rudy Lauwereins; Iuliana P. Radu (CoRR, 2016)

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. - Jianping Wang 006; Sachin S. Sapatnekar; Chris H. Kim; Paul A. Crowell; Steven J. Koester; Supriyo Datta; Kaushik Roy 001; Anand Raghunathan; Xiaobo Sharon Hu; Michael T. Niemier; Azad Naeemi; Chia-Ling Chien; et al. (DAC, 2017)

Beyond-CMOS non-Boolean logic benchmarking: Insights and future directions. - Chenyun Pan; Azad Naeemi (DATE, 2017)

Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean Logic Applications. - Chenyun Pan; Azad Naeemi (CoRR, 2017)

Clocked Magnetostriction-Assisted Spintronic Device Design and Simulation. - Rouhollah Mousavi Iraei; Nickvash Kani; Sourav Dutta; Dmitri E. Nikonov; Sasikanth Manipatruni; Ian A. Young; John T. Heron; Azad Naeemi (CoRR, 2017)

Hybrid piezoelectric-magnetic neurons: a proposal for energy-efficient machine learning. - William Scott; Jonathan Jeffrey; Blake Heard; Dmitri E. Nikonov; Ian A. Young; Sasikanth Manipatruni; Azad Naeemi; Rouhollah Mousavi Iraei (ACM Southeast Regional Conference, 2018)

Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule. - Divya Prasad; Saurabh Sinha; Brian Cline; Steve Moore; Azad Naeemi (DAC, 2018)

Generic system-level modeling and optimization for beyond CMOS device applications. - Victor Huang; Chenyun Pan; Azad Naeemi (ISQED, 2018)

Particle in a Box: An Experiential Environment for Learning Introductory Quantum Mechanics. - Aditya Anupam; Ridhima Gupta; Azad Naeemi; Nassim Jafarinaimi (IEEE Trans. Educ., 2018)

Beyond Motivation and Memorization: Fostering Scientific Inquiry with Games. - Aditya Anupam; Shubhangi Gupta; Azad Naeemi; Nassim Parvin (CHI PLAY (Companion), 2019)

A Mixed Signal Architecture for Convolutional Neural Networks. - Qiuwen Lou; Chenyun Pan; John McGuinness; András Horváth; Azad Naeemi; Michael T. Niemier; Xiaobo Sharon Hu (ACM J. Emerg. Technol. Comput. Syst., 2019)

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper). - Eleonora Testa; Samantha Lubaba Noor; Odysseas Zografos; Mathias Soeken; Francky Catthoor; Azad Naeemi; Giovanni De Micheli (DATE, 2020)

Physics-Based Models for Magneto-Electric Spin-Orbit Logic Circuits. - Hai Li 008; Dmitri E. Nikonov; Chia-Ching Lin; Kerem Yunus Çamsari; Yu-Ching Liao; Chia-Sheng Hsu; Azad Naeemi; Ian A. Young (CoRR, 2021)

Performance Benchmarking of Spin-Orbit Torque Magnetic RAM (SOT-MRAM) for Deep Neural Network (DNN) Accelerators. - Yandong Luo; Piyush Kumar; Yu-Ching Liao; William Hwang; Fen Xue; Wilman Tsai; Shan X. Wang; Azad Naeemi; Shimeng Yu (IMW, 2022)

Roadmap for Unconventional Computing with Nanotechnology. - Giovanni Finocchio; Supriyo Bandyopadhyay; Peng Lin; Gang Pan 001; J. Joshua Yang; Riccardo Tomasello; Christos Panagopoulos; Mario Carpentieri; Vito Puliafito; Johan Åkerman; Hiroki Takesue; Amit Ranjan Trivedi; et al. (CoRR, 2023)

Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis. - Liuting Shang; Azad Naeemi; Chenyun Pan (IEEE Open J. Comput. Soc., 2023)

WIP: Towards a Georgia Tech Semiconductor Experience for Underclassmen. - William L. Schaffer; Ajeet Rohatgi; Azad Naeemi; A. Bruno Frazier (FIE, 2024)

Cross-layer Modeling and Design of Content Addressable Memories in Advanced Technology Nodes for Similarity Search. - Siri Narla; Piyush Kumar; Mohammad Adnaan; Azad Naeemi (CoRR, 2024)

A 5T-2MTJ STT-assisted Spin Orbit Torque based Ternary Content Addressable Memory for Hardware Accelerators. - Siri Narla; Piyush Kumar; Azad Naeemi (CoRR, 2024)

Axon: A Novel Systolic Array Architecture for Improved Run Time and Energy Efficient GeMM and Conv Operation with On-Chip im2col. - Md Mizanur Rahaman Nayan; Ritik Raj; Shaik Gouse Basha; Tushar Krishna; Azad J. Naeemi (DATE, 2025)

HyDra: SOT-CAM Based Vector Symbolic Macro for Hyperdimensional Computing. - Md Mizanur Rahaman Nayan; Che-Kai Liu; Zishen Wan; Arijit Raychowdhury; Azad J. Naeemi (CoRR, 2025)

Content Addressable Memory Design with Reference Resistor for Improved Search Resolution. - Siri Narla; Steven J. Koester; Rebecca A. Dawley; Ageeth A. Bol; Piyush Kumar; Azad Naeemi (CoRR, 2025)