MSDP with ACO: A maximal SRLG disjoint routing algorithm based on ant colony optimization. - Mohammad Javad Rostami; Azadeh Alsadat Emrani Zarandi; Seyed Mohamad Hoseininasab (J. Netw. Comput. Appl., 2012)

Rethinking reverse converter design: From algorithms to hardware components. - Amir Sabbagh Molahosseini; Azadeh Alsadat Emrani Zarandi; Seyed Mostafa Mirhosseini; Mehdi Hosseinzadeh 001 (ISIC, 2014)

Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations. - Azadeh Alsadat Emrani Zarandi; Amir Sabbagh Molahosseini; Mehdi Hosseinzadeh 001; Saeid Sorouri; Samuel Antão; Leonel Sousa (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Area-delay-power-aware adder placement method for RNS reverse converter design. - Azadeh Alsadat Emrani Zarandi; Amir Sabbagh Molahosseini; Leonel Sousa; Mehdi Hosseinzadeh 001; Keivan Navi (LASCAS, 2016)

A Multifunctional Unit for Designing Efficient RNS-Based Datapaths. - Amir Sabbagh Molahosseini; Azadeh Alsadat Emrani Zarandi; Paulo Martins 002; Leonel Sousa (IEEE Access, 2017)

An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form {2k, 2P-1}. - Azadeh Alsadat Emrani Zarandi; Amir Sabbagh Molahosseini; Leonel Sousa; Mehdi Hosseinzadeh 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Towards Efficient Modular Adders based on Reversible Circuits. - Amir Sabbagh Molahosseini; Ailin Asadpoor; Azadeh Alsadat Emrani Zarandi; Leonel Sousa (ISCAS, 2018)

New energy-efficient hybrid wide-operand adder architecture. - Fereshteh Jafarzadehpour; Amir Sabbagh Molahosseini; Azadeh Alsadat Emrani Zarandi; Leonel Sousa (IET Circuits Devices Syst., 2019)

Efficient Modular Adder Designs Based on Thermometer and One-Hot Coding. - Fereshteh Jafarzadehpour; Amir Sabbagh Molahosseini; Azadeh Alsadat Emrani Zarandi; Leonel Sousa (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Multifunctional Unit For Reverse Conversion and Sign Detection Based on The 5-Moduli Set. - Mohsen Mojahed; Amir Sabbagh Molahosseini; Azadeh Alsadat Emrani Zarandi (Comput. Sci., 2021)

Variable Latency Carry Speculative Adders with Input-based Dynamic Configuration. - Hoda Ghabeli; Amir Sabbagh Molahosseini; Azadeh Alsadat Emrani Zarandi; Leonel Sousa (Comput. Electr. Eng., 2021)

Low-Precision Floating-Point Formats: From General-Purpose to Application-Specific. - Amir Sabbagh Molahosseini; Leonel Sousa; Azadeh Alsadat Emrani Zarandi; Hans Vandierendonck (Approximate Computing, 2022)

Effect of the Spectrum Sensing Period on the TCP Performance Over Cognitive Radio Ad-hoc Networks. - Mohammad Mehdi Hassani; Sanaz Pashmforoush; Azadeh Alsadat Emrani Zarandi (Wirel. Pers. Commun., 2022)

uLog: a software-based approximate logarithmic number system for computations on SIMD processors. - Saeedeh Jahanshahi; Amir Sabbagh Molahosseini; Azadeh Alsadat Emrani Zarandi (J. Supercomput., 2023)

An efficient multi-format low-precision floating-point multiplier. - Hadis Ahmadpour Kermani; Azadeh Alsadat Emrani Zarandi (Sustain. Comput. Informatics Syst., 2024)