A Probabilistic Approach to Buffer Insertion. - Vishal Khandelwal; Azadeh Davoodi; Akash Nanavati; Ankur Srivastava 001 (ICCAD, 2003)

Effective graph theoretic techniques for the generalized low power binding problem. - Azadeh Davoodi; Ankur Srivastava 001 (ISLPED, 2003)

High level techniques for power-grid noise immunity. - Azadeh Davoodi; Vishal Khandelwal; Ankur Srivastava 001 (ACM Great Lakes Symposium on VLSI, 2004)

Variability inspired implementation selection problem. - Azadeh Davoodi; Vishal Khandelwal; Ankur Srivastava 001 (ICCAD, 2004)

Efficient statistical timing analysis through error budgeting. - Vishal Khandelwal; Azadeh Davoodi; Ankur Srivastava 001 (ICCAD, 2004)

Wire-length prediction using statistical techniques. - Jennifer L. Wong; Azadeh Davoodi; Vishal Khandelwal; Ankur Srivastava 001; Miodrag Potkonjak (ICCAD, 2004)

Empirical models for net-length probability distribution and applications. - Azadeh Davoodi; Vishal Khandelwal; Ankur Srivastava 001 (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Simultaneous floorplanning and resource binding: a probabilistic approach. - Azadeh Davoodi; Ankur Srivastava 001 (ASP-DAC, 2005)

Wake-up protocols for controlling current surges in MTCMOS-based technology. - Azadeh Davoodi; Ankur Srivastava 001 (ASP-DAC, 2005)

Variability-Driven Buffer Insertion Considering Correlations. - Azadeh Davoodi; Ankur Srivastava 001 (ICCD, 2005)

Probabilistic dual-Vth leakage optimization under variability. - Azadeh Davoodi; Ankur Srivastava 001 (ISLPED, 2005)

Voltage scheduling under unpredictabilities: a risk management paradigm. - Azadeh Davoodi; Ankur Srivastava 001 (ACM Trans. Design Autom. Electr. Syst., 2005)

Power-driven simultaneous resource binding and floorplanning: a probabilistic approach. - Azadeh Davoodi; Ankur Srivastava 001 (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Simultaneous Vt selection and assignment for leakage optimization. - Vishal Khandelwal; Azadeh Davoodi; Ankur Srivastava 001 (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Probabilistic evaluation of solutions in variability-driven optimization. - Azadeh Davoodi; Ankur Srivastava 001 (ISPD, 2006)

FPGA Dynamic Power Minimization through Placement and Routing Constraints. - Li Wang 012; Matthew French; Azadeh Davoodi; Deepak Agarwal (EURASIP J. Embed. Syst., 2006)

Probabilistic Evaluation of Solutions in Variability-Driven Optimization. - Azadeh Davoodi; Vishal Khandelwal; Ankur Srivastava 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A statistical methodology for wire-length prediction. - Jennifer L. Wong; Azadeh Davoodi; Vishal Khandelwal; Ankur Srivastava 001; Miodrag Potkonjak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Effective techniques for the generalized low-power binding problem. - Azadeh Davoodi; Ankur Srivastava 001 (ACM Trans. Design Autom. Electr. Syst., 2006)

Optimization Schemes for Variability-Driven VLSI Design Automation. - Azadeh Davoodi (2006)

Statistical timing analysis using Kernel smoothing. - Jennifer L. Wong; Azadeh Davoodi; Vishal Khandelwal; Ankur Srivastava 001; Miodrag Potkonjak (ICCD, 2007)

Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations. - Jungseob Lee; Azadeh Davoodi (ISCAS, 2007)

Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence. - Ashish Dobhal; Vishal Khandelwal; Azadeh Davoodi; Ankur Srivastava 001 (VLSI Design, 2007)

PaRS: fast and near-optimal grid-based cell sizing for library-based design. - Tai-Hsuan Wu; Azadeh Davoodi (ICCAD, 2008)

Adjustment-based modeling for statistical static timing analysis with high dimension of variability. - Lin Xie; Azadeh Davoodi; Jun Zhang; Tai-Hsuan Wu (ICCAD, 2008)

SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement. - Anuj Kumar; Tai-Hsuan Wu; Azadeh Davoodi (ICCD, 2008)

A Dual-Vt low leakage SRAM array robust to process variations. - Jungseob Lee; Lin Xie; Azadeh Davoodi (ISCAS, 2008)

Fast and accurate statistical static timing analysis with skewed process parameter variation. - Lin Xie; Azadeh Davoodi (IET Circuits Devices Syst., 2008)

A Parallel and Randomized Algorithm for Large-Scale Discrete Dual-Vt Assignment and Continuous Gate Sizing. - Tai-Hsuan Wu; Lin Xie; Azadeh Davoodi (J. Low Power Electron., 2008)

Robust Estimation of Timing Yield With Partial Statistical Information on Process Variations. - Lin Xie; Azadeh Davoodi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Variability Driven Gate Sizing for Binning Yield Optimization. - Azadeh Davoodi; Ankur Srivastava 001 (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Bound-based identification of timing-violating paths under variability. - Lin Xie; Azadeh Davoodi (ASP-DAC, 2009)

GRIP: scalable 3D global routing using integer programming. - Tai-Hsuan Wu; Azadeh Davoodi; Jeffrey T. Linderoth (DAC, 2009)

Statistical static timing analysis considering leakage variability in power gated designs. - Michael J. Anderson; Azadeh Davoodi; Jungseob Lee; Abhishek A. Sinkar; Nam Sung Kim (ISLPED, 2009)

False Path Aware Timing Yield Estimation under Variability. - Lin Xie; Azadeh Davoodi; Kewal K. Saluja; Abhishek A. Sinkar (VTS, 2009)

PaRS: Parallel and Near-Optimal Grid-Based Cell Sizing for Library-Based Design. - Tai-Hsuan Wu; Azadeh Davoodi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Adjustment-Based Modeling for Timing Analysis Under Variability. - Lin Xie; Azadeh Davoodi; Jun Zhang; Tai-Hsuan Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors. - Dongkeun Oh; Nam Sung Kim; Charlie Chung-Ping Chen; Azadeh Davoodi; Yu Hen Hu (ASP-DAC, 2010)

A parallel integer programming approach to global routing. - Tai-Hsuan Wu; Azadeh Davoodi; Jeffrey T. Linderoth (DAC, 2010)

Representative path selection for post-silicon timing prediction under variability. - Lin Xie; Azadeh Davoodi (DAC, 2010)

Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. - Lin Xie; Azadeh Davoodi; Kewal K. Saluja (DAC, 2010)

Trace signal selection to enhance timing and logic visibility in post-silicon validation. - Hamid Shojaei; Azadeh Davoodi (ICCAD, 2010)

A pareto-algebraic framework for signal power optimization in global routing. - Hamid Shojaei; Tai-Hsuan Wu; Azadeh Davoodi; Twan Basten (ISLPED, 2010)

Power-driven global routing for multi-supply voltage domains. - Tai-Hsuan Wu; Azadeh Davoodi; Jeff T. Linderoth (DATE, 2011)

Congestion analysis for global routing via integer programming. - Hamid Shojaei; Azadeh Davoodi; Jeffrey T. Linderoth (ICCAD, 2011)

GRIP: Global Routing via Integer Programming. - Tai-Hsuan Wu; Azadeh Davoodi; Jeffrey T. Linderoth (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Bound-Based Statistically-Critical Path Extraction Under Process Variations. - Lin Xie; Azadeh Davoodi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Confidentiality preserving integer programming for global routing. - Hamid Shojaei; Azadeh Davoodi; Parmeswaran Ramanathan (DAC, 2012)

Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations. - Min Li; Azadeh Davoodi; Lin Xie (DATE, 2012)

Post-Silicon Failing-Path Isolation Incorporating the Effects of Process Variations. - Lin Xie; Azadeh Davoodi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Planning for local net congestion in global routing. - Hamid Shojaei; Azadeh Davoodi; Jeffrey T. Linderoth (ISPD, 2013)

A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection. - Azadeh Davoodi; Min Li; Mohammad Tehranipoor (IEEE Des. Test, 2013)

A fast and scalable multidimensional multiple-choice knapsack heuristic. - Hamid Shojaei; Twan Basten; Marc Geilen; Azadeh Davoodi (ACM Trans. Design Autom. Electr. Syst., 2013)

Collaborative Multiobjective Global Routing. - Hamid Shojaei; Azadeh Davoodi; Twan Basten (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Power-Driven Global Routing for Multisupply Voltage Domains. - Tai-Hsuan Wu; Azadeh Davoodi; Jeffrey T. Linderoth (VLSI Design, 2013)

Multi-mode trace signal selection for post-silicon debug. - Min Li; Azadeh Davoodi (ASP-DAC, 2014)

A Hybrid Approach for Fast and Accurate Trace Signal Selection for Post-Silicon Debug. - Min Li; Azadeh Davoodi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

On using control signals for word-level identification in a gate-level netlist. - Edward Tashjian; Azadeh Davoodi (DAC, 2015)

Online and Operand-Aware Detection of Failures Utilizing False Alarm Vectors. - Amir Yazdanbakhsh; David J. Palframan; Azadeh Davoodi; Nam Sung Kim; Mikko H. Lipasti (ACM Great Lakes Symposium on VLSI, 2015)

Automatic die placement and flexible I/O assignment in 2.5D IC design. - Daniel P. Seemuth; Azadeh Davoodi; Katherine Morrow (ISQED, 2015)

Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes. - Azadeh Davoodi; Jiang Hu; Muhammet Mustafa Ozdal; Cliff C. N. Sze (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

A procedure for improving the distribution of congestion in global routing. - Daohang Shi; Azadeh Davoodi; Jeffrey T. Linderoth (DATE, 2016)

Are proximity attacks a threat to the security of split manufacturing of integrated circuits? - Jonathon Magaña; Daohang Shi; Azadeh Davoodi (ICCAD, 2016)

Preface to Special Section on New Physical Design Techniques for the Next Generation of Integration Technology. - Evangeline F. Y. Young; Azadeh Davoodi (ACM Trans. Design Autom. Electr. Syst., 2016)

Flexible interconnect in 2.5D ICs to minimize the interposer's metal layers. - Daniel P. Seemuth; Azadeh Davoodi; Katherine Morrow (ASP-DAC, 2017)

TraPL: Track Planning of Local Congestion for Global Routing. - Daohang Shi; Azadeh Davoodi (DAC, 2017)

Technology mapping with all spin logic. - Boyu Zhang 001; Azadeh Davoodi (DATE, 2017)

Improving Detailed Routability and Pin Access with 3D Monolithic Standard Cells. - Daohang Shi; Azadeh Davoodi (ISPD, 2017)

Dynamic Planning of Local Congestion From Varying-Size Vias for Global Routing Layer Assignment. - Daohang Shi; Edward Tashjian; Azadeh Davoodi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Are Proximity Attacks a Threat to the Security of Split Manufacturing of Integrated Circuits? - Jonathon Magaña; Daohang Shi; Jackson Melchert; Azadeh Davoodi (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Analysis of security of split manufacturing using machine learning. - Boyu Zhang 001; Jonathon Crandall Magaña; Azadeh Davoodi (DAC, 2018)

A Comparative Study of Local Net Modeling Using Machine Learning. - Jackson Melchert; Boyu Zhang 001; Azadeh Davoodi (ACM Great Lakes Symposium on VLSI, 2018)

A Mixture of Expert Approach for Low-Cost Customization of Deep Neural Networks. - Boyu Zhang 001; Azadeh Davoodi; Yu Hen Hu (CoRR, 2018)

Design Rule Violation Hotspot Prediction Based on Neural Network Ensembles. - Wei Zeng 015; Azadeh Davoodi; Yu Hen Hu (CoRR, 2018)

Exploring Energy and Accuracy Tradeoff in Structure Simplification of Trained Deep Neural Networks. - Boyu Zhang 001; Azadeh Davoodi; Yu Hen Hu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

Dynamic Reconfiguration of CNNs for Input-Dependent Approximation. - Maedeh Hemmat; Azadeh Davoodi (ISQED, 2019)

Efficient Inference of CNNs via Channel Pruning. - Boyu Zhang 001; Azadeh Davoodi; Yu Hen Hu (CoRR, 2019)

Power-efficient ReRAM-aware CNN model generation. - Maedeh Hemmat; Azadeh Davoodi (Integr., 2019)

Analysis of Security of Split Manufacturing Using Machine Learning. - Wei Zeng 015; Boyu Zhang 001; Azadeh Davoodi (IEEE Trans. Very Large Scale Integr. Syst., 2019)

CHaPR: Efficient Inference of CNNs via Channel Pruning. - Boyu Zhang 001; Azadeh Davoodi; Yu Hen Hu (COINS, 2020)

CAP'NN: Class-Aware Personalized Neural Network Inference. - Maedeh Hemmat; Joshua San Miguel; Azadeh Davoodi (DAC, 2020)

Explainable DRC Hotspot Prediction with Random Forest and SHAP Tree Explainer. - Wei Zeng 015; Azadeh Davoodi; Rasit Onur Topaloglu (DATE, 2020)

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. - Shubham Rai; Walter Lau Neto; Yukio Miyasaka; Xinpei Zhang; Mingfei Yu; Qingyang Yi; Masahiro Fujita; Guilherme B. Manske; Matheus F. Pontes; Leomar S. da Rosa; Marilton S. de Aguiar; Paulo F. Butzen; et al. (DATE, 2021)

Sampling-Based Approximate Logic Synthesis: An Explainable Machine Learning Approach. - Wei Zeng 015; Azadeh Davoodi; Rasit Onur Topaloglu (ICCAD, 2021)

Lorax: Machine Learning-Based Oracle Reconstruction With Minimal I/O Patterns. - Wei Zeng 015; Azadeh Davoodi; Rasit Onur Topaloglu (ISVLSI, 2021)

A Mixture of Experts Approach for Low-Cost DNN Customization. - Boyu Zhang 001; Azadeh Davoodi; Yu Hen Hu (IEEE Des. Test, 2021)

AirNN: A Featherweight Framework for Dynamic Input-Dependent Approximation of CNNs. - Maedeh Hemmat; Joshua San Miguel; Azadeh Davoodi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

$ text{Edge}^{n}$ AI: Distributed Inference with Local Edge Devices and Minimal Latency. - Maedeh Hemmat; Azadeh Davoodi; Yu Hen Hu (ASP-DAC, 2022)

CAP'NN: A Class-aware Framework for Personalized Neural Network Inference. - Maedeh Hemmat; Joshua San Miguel; Azadeh Davoodi (ACM Trans. Embed. Comput. Syst., 2022)

Neural Network Partitioning for Fast Distributed Inference. - Robert Viramontes; Azadeh Davoodi (ISQED, 2023)

Block Pruning for Enhanced Efficiency in Convolutional Neural Networks. - Cheng-En Wu; Azadeh Davoodi; Yu Hen Hu (CoRR, 2023)

ObfusX: Routing obfuscation with explanatory analysis of a machine learning attack. - Wei Zeng 015; Azadeh Davoodi; Rasit Onur Topaloglu (Integr., 2023)

Introduction to Special Section on FPT'20. - Oliver Sinnen; Qiang Liu 011; Azadeh Davoodi (ACM Trans. Reconfigurable Technol. Syst., 2023)

Efficient and Effective Neural Networks for Automatic Test Pattern Generation. - Lizi Zhang; Azadeh Davoodi (MLCAD, 2024)

DIME: Distributed Inference Model Estimation for Minimizing Profiled Latency. - Robert Viramontes; Azadeh Davoodi (SMARTCOMP, 2024)

Static IR Drop Prediction with Attention U-Net and Saliency-Based Explainability. - Lizi Zhang; Azadeh Davoodi (CoRR, 2024)

Static IR Drop Prediction with Limited Data from Real Designs. - Lizi Zhang; Azadeh Davoodi (ASP-DAC, 2025)

CADI: Carbon-Aware Distributed Inference. - Robert Viramontes; Azadeh Davoodi (COINS, 2025)

ReBERT: LLM for Gate-Level to Word-Level Reverse Engineering. - Lizi Zhang; Azadeh Davoodi; Rasit Onur Topaloglu (DATE, 2025)

FreDDI: Frequency-Driven DNN Partitioning in Distributed Inference. - Robert Viramontes; Azadeh Davoodi (SMARTCOMP, 2025)