Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory. - Adrià Armejach; Azam Seyedi; J. Rubén Titos Gil; Ibrahim Hur; Adrián Cristal; Osman S. Unsal; Mateo Valero (PACT, 2011)

Circuit design of a dual-versioning L1 data cache for optimistic concurrency. - Azam Seyedi; Adrià Armejach; Adrián Cristal; Osman S. Unsal; Ibrahim Hur; Mateo Valero (ACM Great Lakes Symposium on VLSI, 2011)

Novel SRAM bias control circuits for a low power L1 data cache. - Azam Seyedi; Adrià Armejach; Adrián Cristal; Osman S. Unsal; Mateo Valero (NORCHIP, 2012)

Circuit design of a dual-versioning L1 data cache. - Azam Seyedi; Adrià Armejach; Adrián Cristal; Osman S. Unsal; Ibrahim Hur; Mateo Valero (Integr., 2012)

Circuit design of a novel adaptable and reliable L1 data cache. - Azam Seyedi; Gulay Yalcin; Osman S. Unsal; Adrián Cristal (ACM Great Lakes Symposium on VLSI, 2013)

Flexicache: Highly Reliable and Low Power Cache under Supply Voltage Scaling. - Gulay Yalcin; Azam Seyedi; Osman S. Unsal; Adrián Cristal (CARLA, 2014)

NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs. - Azam Seyedi; Vasileios Karakostas; Stefan Cosemans; Adrián Cristal; Mario Nemirovsky; Osman S. Unsal (NANOARCH, 2015)

Circuit designs for increasing reliability and reducing energy. - Azam Seyedi (2016)

Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications. - Azam Seyedi; Snorre Aunet; Per Gunnar Kjeldsberg (NORCAS, 2019)

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements. - Azam Seyedi; Snorre Aunet; Per Gunnar Kjeldsberg (IEEE Access, 2022)