An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters. - Masataka Matsui; Hiroshi Momose; Yukihiro Urakawa; Takeo Maeda; Azuma Suzuki; Nobuaki Urakawa; Katsuhiko Sato; Jun'ichi Matsunaga; Kiyofumi Ochii (IEEE J. Solid State Circuits, 1989)

DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs. - Osamu Hirabayashi; Azuma Suzuki; Tomoaki Yabe; Atsushi Kawasumi; Yasuhisa Takeyama; Keiichi Kushida; Akihito Tohata; Nobuaki Otsuka (ITC, 2002)

A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver. - Osamu Hirabayashi; Atsushi Kawasumi; Azuma Suzuki; Yasuhisa Takeyama; Keiichi Kushida; Takahiko Sasaki; Akira Katayama; Gou Fukano; Yuki Fujimura; Takaaki Nakazato; Yasushi Shizuki; Natsuki Kushiyama; et al. (ISSCC, 2009)

A 0.7 V Single-Supply SRAM With 0.495 µm2 Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme. - Keiichi Kushida; Azuma Suzuki; Gou Fukano; Atsushi Kawasumi; Osamu Hirabayashi; Yasuhisa Takeyama; Takahiko Sasaki; Akira Katayama; Yuki Fujimura; Tomoaki Yabe (IEEE J. Solid State Circuits, 2009)

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS. - Yuki Fujimura; Osamu Hirabayashi; Takahiko Sasaki; Azuma Suzuki; Atsushi Kawasumi; Yasuhisa Takeyama; Keiichi Kushida; Gou Fukano; Akira Katayama; Yusuke Niki; Tomoaki Yabe (ISSCC, 2010)

A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access. - Keiichi Kushida; Osamu Hirabayashi; Fumihiko Tachibana; Hiroyuki Hara; Atsushi Kawasumi; Azuma Suzuki; Yasuhisa Takeyama; Yuki Fujimura; Yusuke Niki; Miyako Shizuno; Shinichi Sasaki; Tomoaki Yabe (A-SSCC, 2011)

A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers. - Yusuke Niki; Atsushi Kawasumi; Azuma Suzuki; Yasuhisa Takeyama; Osamu Hirabayashi; Keiichi Kushida; Fumihiko Tachibana; Yuki Fujimura; Tomoaki Yabe (IEEE J. Solid State Circuits, 2011)

A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit. - Fumihiko Tachibana; Osamu Hirabayashi; Yasuhisa Takeyama; Miyako Shizuno; Atsushi Kawasumi; Keiichi Kushida; Azuma Suzuki; Yusuke Niki; Shinichi Sasaki; Tomoaki Yabe; Yasuo Unekawa (IEEE J. Solid State Circuits, 2014)