Development and testing of a cross-sectional area measurement tool for evaluating vein size. - Brian D. Davison 002; K. Yeshwant; Ron Kikinis; J. Rolnick; Kelly H. Zou; B. Chung; E. K. Yucel (Comput. Biol. Medicine, 2005)

Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology. - B. Chung; J. B. Kuo (ISCAS, 2006)

Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique. - B. Chung; J. B. Kuo (PATMOS, 2006)

Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application. - B. Chung; J. B. Kuo (Integr., 2008)