Comprehensive Feasibility Study of Single FIN Transistors for Scaling Both Switching Energy and Device Footprint. - H. Fukutome; K. Suh; W. Kim; Y. Moriyama; S. Kang; B. Eom; J. Kim; C. Yoon; W. Kwon; Y. Chung; Y. Nam; Y. Kim; et al. (VLSI Technology and Circuits, 2022)

Demonstration of Logic-Block Performance-Power Gain by 1st Generation Back Side Power Delivery Network for SoC and HPC Applications Beyond 2nm Node. - H. Fukutome; J. Kim; Joonghan Shin; Youngsoo Lee; Youngsoo Park; Do-Youn Oh; Seung-Hoon Chae; B. Eom; You Nam; Minseong Lee; Sanghyun Ha; Eun-Ae Chung; et al. (VLSI Technology and Circuits, 2024)

Demonstration of Logic-Block Performance-Power-Area Gain by 1st Generation Back Side Power Delivery Network for SoC and HPC Applications Beyond 2 nm Node. - H. Fukutome; J. Kim; Joonghan Shin; J. Kim; Youngsoo Lee; S. Chae; B. Eom; Y. S. Nam; Minseong Lee; Sanghyun Ha; E. G. Chung; Sung-Hoon Lee; et al. (CICC, 2025)