Analysis of implant parameters in high voltage TRIPLE RESURF LDMOS for advanced SoC applications. - B. Jhnanesh Somayaji; M. S. Bhat 001 (ISED, 2016)

Triple Reduced Surface Field Drain Extended MOS Device Design and Its RF Performance Evaluation for Sub-Micron RF SoC Platform. - B. Jhnanesh Somayaji; M. S. Bhat 001 (J. Low Power Electron., 2017)