An Efficient Test Pattern Generation Scheme for an On Chip BIST. - B. K. S. V. L. Varaprasad; L. M. Patnaik; Hirisave S. Jamadagni; V. K. Agrawal (VLSI Design, 2001)

A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits. - B. K. S. V. L. Varaprasad; Lalit M. Patnaik; Hirisave S. Jamadagni; V. K. Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

A New ATPG Technique (ExpoTan) for Testing Analog Circuits. - B. K. S. V. L. Varaprasad; Lalit M. Patnaik; Hirisave S. Jamadagni; V. K. Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Radiation Hardened by Design Latches - A Review and SEU Fault Simulations. - Faisal Mustafa Sajjade; Neeraj Kumar Goyal; B. K. S. V. L. Varaprasad; Ravindra Moogina (Microelectron. Reliab., 2018)

REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architecture. - Raghunandana K. K; B. K. S. V. L. Varaprasad; Matteo Sonza Reorda; Virendra Singh (ISVLSI, 2022)

TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture. - Raghunandana K. K; B. K. S. V. L. Varaprasad; Matteo Sonza Reorda; Virendra Singh (IOLTS, 2023)