Continuous representation of the performance of a CMOS library. - B. Lasbouygues; Joel Schindler; Sylvain Engels; Philippe Maurine; Nadine Azémard; Daniel Auvergne (ESSCIRC, 2003)

Temperature Dependence in Low Power CMOS UDSM Process. - B. Lasbouygues; Robin Wilson; Philippe Maurine; Nadine Azémard; Daniel Auvergne (PATMOS, 2004)

Physical Extension of the Logical Effort Model. - B. Lasbouygues; Robin Wilson; Philippe Maurine; Nadine Azémard; Daniel Auvergne (PATMOS, 2004)

Temperature Dependency in UDSM Process. - B. Lasbouygues; Robin Wilson; Nadine Azémard; Philippe Maurine (PATMOS, 2005)

Timing analysis in presence of supply voltage and temperature variations. - B. Lasbouygues; Robin Wilson; Nadine Azémard; Philippe Maurine (ISPD, 2006)

Logical effort model extension to propagation delay representation. - B. Lasbouygues; Sylvain Engels; Robin Wilson; Philippe Maurine; Nadine Azémard; Daniel Auvergne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Temperature and voltage aware timing analysis: application to voltage drops. - B. Lasbouygues; Robin Wilson; Nadine Azémard; Philippe Maurine (DATE, 2007)

Temperature- and Voltage-Aware Timing Analysis. - B. Lasbouygues; Robin Wilson; Nadine Azémard; Philippe Maurine (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)