An Efficient Online Mileage Indicator by Using Sensors for New Generation Automobiles. - B. Naresh Kumar Reddy; M. Naraimhulu; S. V. Sai Prasad; K. Khaja Babu (ADCONS, 2013)

An efficient approach for design and testing of FPGA programming using Lab VIEW. - B. Naresh Kumar Reddy; N. Suresh; Janjhyam Venkata Naga Ramesh; T. Pavithra; Y. Krupa Bahulya; Pranose J. Edavoor; S. Janaki Ram (ICACCI, 2015)

Poster: An Efficient Low Power & High Performance in MPSOC. - K. Jayasree; B. Naresh Kumar Reddy; B. Srinuvasu Kumar; Janjhyam Venkata Naga Ramesh; Pranose J. Edavoor; Mohd Kashif Zia Ansari (WCI, 2015)

A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core. - B. Naresh Kumar Reddy; M. H. Vasantha; Kumar Y. B. Nithin (ISVLSI, 2016)

System level fault-tolerance core mapping and FPGA-based verification of NoC. - Naresh Kumar Reddy Becchu; Vasantha Moodabettu Harishchandra; Nithin Kumar Yernad Balachandra (Microelectron. J., 2017)

High-performance and energy-efficient fault-tolerance core mapping in NoC. - Naresh Kumar Reddy Beechu; Vasantha Moodabettu Harishchandra; Nithin Kumar Yernad Balachandra (Sustain. Comput. Informatics Syst., 2017)

A Technique to Reduce the Capacitor Size in Two Stage Miller Compensated Opamp. - Rajasekhar Nagulapalli; Khaled Hayatleh; Steve Barker; Saddam Zourob; Nabil Yassine; B. Naresh Kumar Reddy (ICCCNT, 2018)

High Performance Circuit Techniques for Nueral Front-End Design in 65nm CMOS. - Rajasekhar Nagulapalli; Khaled Hayatleh; Steve Barker; Saddam Zourob; Nabil Yassine; B. Naresh Kumar Reddy (ICCCNT, 2018)

A 31 ppm/° C Pure CMOS Bandgap Reference by Exploiting Beta-Multiplier. - Rajasekhar Nagulapalli; Khaled Hayatleh; Steve Barker; Saddam Zourob; Nabil Yassine; B. Naresh Kumar Reddy (VDAT, 2018)

An Energy-Efficient Core Mapping Algorithm on Network on Chip (NoC). - B. Naresh Kumar Reddy; Sireesha (VDAT, 2018)

An energy-efficient fault-aware core mapping in mesh-based network on chip systems. - Naresh Kumar Reddy Beechu; Vasantha Moodabettu Harishchandra; Nithin Kumar Yernad Balachandra (J. Netw. Comput. Appl., 2018)

Hardware implementation of fault tolerance NoC core mapping. - Naresh Kumar Reddy Beechu; Vasantha Moodabettu Harishchandra; Nithin Kumar Yernad Balachandra (Telecommun. Syst., 2018)

Energy-Aware and Reliability-Aware Mapping for NoC-Based Architectures. - Naresh Kumar Reddy Beechu; Vasantha Moodabettu Harishchandra; Nithin Kumar Yernad Balachandra (Wirel. Pers. Commun., 2018)

A Low Power Miller Compensation Technique for Two Stage Op-amp in 65nm CMOS Technology. - Rajasekhar Nagulapalli; Khaled Hayatleh; Steve Barker; B. Naresh Kumar Reddy; B. Seetharamulu (ICCCNT, 2019)

A High Frequency CMRR improvement technique for Differential Amplifiers in 45nm CMOS. - Rajasekhar Nagulapalli; Khaled Hayatleh; Steve Barker; B. Naresh Kumar Reddy; B. Seetharamulu (ICCCNT, 2019)

A Bi-Level Cascaded Ensemble Framework for Effective Disease Diagnosis. - Ramalingaswamy Cheruku; Pradeep Kumar Nalluri; Krishna Yogeshwar G. Gopi; J. B. S. Charan; V. Naga Sanketh; Nareshkumar Reddy Beechu (TENCON, 2019)

SRAM cell with better read and write stability with Minimum area. - B. Naresh Kumar Reddy; K. Sarangam; T. Veeraiah; Ramalingaswamy Cheruku (TENCON, 2019)

Performance constrained multi-application network on chip core mapping. - B. Naresh Kumar Reddy; Dharavath Kishan; B. Veena Vani (Int. J. Speech Technol., 2019)

A Single BJT 10.2 ppm/°C Bandgap Reference in 45nm CMOS Technology. - Rajasekhar Nagulapalli; Khaled Hayatleh; Steve Barker; B. Naresh Kumar Reddy (ICCCNT, 2020)

A two-stage opamp frequency Compensation technique by splitting the 2nd stage. - Rajasekhar Nagulapalli; Khaled Hayatleh; Steve Barker; B. Naresh Kumar Reddy (ICCCNT, 2020)

Deep Learning for Sentiment Analysis Based on Customer Reviews. - B. Seetharamulu; B. Naresh Kumar Reddy; K. Bramha Naidu (ICCCNT, 2020)

An efficient design and implementation of Vedic multiplier in quantum-dot cellular automata. - B. Naresh Kumar Reddy; B. Veena Vani; G. Bhavya Lahari (Telecommun. Syst., 2020)

A Highly Secured QoS Aware Routing Algorithm for Software Defined Vehicle Ad-Hoc Networks Using Optimal Trust Management Scheme. - Shakeel Ahmed; N. V. K. Ramesh; B. Naresh Kumar Reddy (Wirel. Pers. Commun., 2020)

Energy Efficient and High Performance Modified Mesh based 2-D NoC Architecture. - B. Naresh Kumar Reddy; Subrat Kar (HPSR, 2021)

Identification of Tomato Crop Diseases Using Neural Networks-CNN. - N. V. K. Ramesh; Mohanpradeep Reddy B; Bhavya Deepika B; N. Suresh; K. Raghava Rao; B. Naresh Kumar Reddy (ICCCNT, 2021)

An Efficient Application Core Mapping Algorithm for Wireless Network-an-Chip. - B. Naresh Kumar Reddy; Subrat Kar (PRDC, 2021)

Machine Learning Techniques for the Prediction of NoC Core Mapping Performance. - B. Naresh Kumar Reddy; Subrat Kar (PRDC, 2021)

Hardware Implementation of an efficient FIR filter for ECG Signal Denoising Application. - Ajaydas. U. R; B. Naresh Kumar Reddy; Alex James 001 (ICECS 2022, 2022)

Fault-Tolerant Core Mapping for NoC based architectures with improved Performance and Energy Efficiency. - B. Naresh Kumar Reddy; Alex James 001; Aruru Sai Kumar (ICECS 2022, 2022)

Performance evaluation of modified mesh-based NoC architecture. - B. Naresh Kumar Reddy; Subrat Kar (Comput. Electr. Eng., 2022)

Performance and communication energy constrained embedded benchmark for fault tolerant core mapping onto NoC architectures. - Aruru Sai Kumar; T. V. K. Hanumantha Rao; B. Naresh Kumar Reddy (Int. J. Ad Hoc Ubiquitous Comput., 2022)

An FPGA and ASIC Implementation of Cubing Architecture. - B. Naresh Kumar Reddy; B. Seetharamulu; G. Siva Krishna; B. Veena Vani (Wirel. Pers. Commun., 2022)

An Efficient Smart Gas Detecting System using MQ9 Sensor. - B. Naresh Kumar Reddy; Tharakeshwar Appala; B. Veena Vani (ICCCNT, 2023)

Accelerating Sorting Performance on FPGA: Combining Quick Sort and Heap Sort through Hybrid Pipelining. - B. Naresh Kumar Reddy; K. Sarangam; Sushmita Dandeliya; S. Pavan Sai Naidu; Naveen Kumar P (iSES, 2023)

An Efficient Real-Time Embedded Application Mapping for NoC Based Multiprocessor System on Chip. - Aruru Sai Kumar; B. Naresh Kumar Reddy (Wirel. Pers. Commun., 2023)

Bat Optimization Model for Electric Vehicle Route Optimization Under Time-of-Use Electricity Pricing. - B. Veena Vani; Dharavath Kishan; Md. Waseem Ahmad; B. Naresh Kumar Reddy (Wirel. Pers. Commun., 2023)

Using advanced distributed energy efficient clustering increasing the network lifetime in wireless sensor networks. - K. Raghava Rao; B. Naresh Kumar Reddy; Aruru Sai Kumar (Soft Comput., 2023)

Enhanced PSO-Integrated Machine Learning for Launch Vehicle Engine Temperature and Pressure Monitoring for Risk Prediction. - Kola Balavani; V. Akshara; E. Venkata Sandeep; M. Charan Sai; K. Raghava Rao; B. Naresh Kumar Reddy (ICCCNT, 2024)

An Area-Efficient VLSI Architecture with Ladner-Fischer PPA for High-Speed Pseudo-Random Bit Generation. - Sakkthi Saranya; P. Maran; Sita Devi Bharatula; B. Naresh Kumar Reddy (ICCCNT, 2024)

Design and Implementation of an FPGA-based Emulator Circuit for MLP using Memristors. - B. Naresh Kumar Reddy; Srinivasulu Jogi; Sarangam K (VDAT, 2024)

Optimizing Task Scheduling in Multi-thread Real-Time Systems using Augmented Particle Swarm Optimization. - B. Naresh Kumar Reddy; Y. Charan Krishna; P. Naga Satya Nitish; Sitadevi Bharatula (VLSID, 2024)

An efficient battery swapping and charging mechanism for electric vehicles using bat algorithm. - B. Veena Vani; Dharavath Kishan; Md. Waseem Ahmad; B. Naresh Kumar Reddy (Comput. Electr. Eng., 2024)

Evaluating the effectiveness of Bat optimization in an adaptive and energy-efficient network-on-chip routing framework. - B. Naresh Kumar Reddy; Aruru Sai Kumar (J. Parallel Distributed Comput., 2024)

Classification of non-small cell lung cancers using deep convolutional neural networks. - Shaik Ummay Atiya; N. V. K. Ramesh; B. Naresh Kumar Reddy (Multim. Tools Appl., 2024)

Developing an adaptive active sleep energy efficient method in heterogeneous wireless sensor network. - M. Sree Chandana; K. Raghava Rao; B. Naresh Kumar Reddy (Multim. Tools Appl., 2024)

Enhancing Reliability and Energy Efficiency in Many-Core Processors Through Fault-Tolerant Network-on-Chip. - B. Naresh Kumar Reddy; Md. Zia Ur Rahman 001; Aimé Lay-Ekuakille (IEEE Trans. Netw. Serv. Manag., 2024)

Enhancing Reliability and Energy Efficiency in Network-on-Chip Architectures through Hybrid Sorting Algorithm-Based Core Mapping. - B. Naresh Kumar Reddy; Srinivasulu Jogi; Y. Charan Krishna (VLSID, 2025)

Analyzing Fully Depleted SOI NC-MOSFET for Enhanced Bio-Sensor and Digital Circuit Applications. - Vydha Pradeep Kumar; Deepak Kumar Panda; Aruru Sai Kumar; B. Naresh Kumar Reddy; Ch. Rama Prakasha Reddy (IET Circuits Devices Syst., 2025)

Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability. - Aswin Sreekumar; Bolupadra Sai Shankar; B. Naresh Kumar Reddy (Integr., 2025)

Design and analysis of faithful parallel mean filter using approximate adders and 4:2 compressors for low-power VLSI architectures. - K. N. Vijeyakumar; Talluri Vineel Jessy; Saranya Karunamurthi; B. Naresh Kumar Reddy (Integr., 2025)

An efficient routing mechanism for VANETs in SDN with hybrid meta-heuristic algorithm. - Shakeel Ahmed; N. V. K. Ramesh; B. Naresh Kumar Reddy (Telecommun. Syst., 2025)