Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs. - B. P. Harish; Navakanta Bhat; Mahesh B. Patil (ICCTA, 2007)

On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology. - B. P. Harish; Navakanta Bhat; Mahesh B. Patil (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Hybrid-CV Modeling for Estimating the Variability in Dynamic Power. - B. P. Harish; Navakanta Bhat; Mahesh B. Patil (J. Low Power Electron., 2008)

Bridging Technology-CAD and Design-CAD for Variability Aware Nano-CMOS Circuits. - B. P. Harish; Navakanta Bhat; Mahesh B. Patil (ISCAS, 2009)

Analytical Modeling of Process Variability in Subthreshold Regime for Ultra Low Power Applications. - Anala M.; B. P. Harish (APCCAS, 2018)

An Integrated MaxFit Genetic Algorithm-SPICE Framework for 2-Stage Op-Amp Design Automation. - Harsha M. V.; B. P. Harish (ISVLSI, 2018)

Process Variation-Aware Analytical Modeling of Subthreshold Leakage Power. - Anala M.; B. P. Harish (PATMOS, 2019)

Dynamic Supply Voltage Level Generation for Minimum Energy Real Time Tasks using Geometric Programming. - H. T. Manohara; B. P. Harish (SoCC, 2019)

Artificial Neural Network Model for Design Optimization of 2-stage Op-amp. - Harsha M. V.; B. P. Harish (VDAT, 2020)

Process-induced variability modeling of subthreshold leakage power considering device stacking. - Anala M. Reddy; B. P. Harish (Int. J. Circuit Theory Appl., 2020)

A Novel Feasibility Test for Energy Minimization of Real-Time Mixed Task Sets for DVS-Enabled Uniprocessor System. - H. T. Manohara; B. P. Harish (J. Circuits Syst. Comput., 2022)

Integrated AWA fitness PSO-SPICE framework for automated design and optimisation of analogue and mixed-signal ICs. - Harsha Maddur Venkataswamy; B. P. Harish (Int. J. Artif. Intell. Soft Comput., 2024)