Power and area calibration of switch arbiter for high speed switch control and scheduling in network-on-chip. - Sangeeta Singh; J. V. R. Ravindra; B. Rajendra Naik (ISOCC, 2016)

Analysis of Crosstalk Noise for Coupled Microstrip Interconnect Models in High-Speed PCB Design. - Raju Mudavath; B. Rajendra Naik; Bhaskar Gugulothu (ICEIC, 2019)

High performance area efficient DA based FIR filter for concurrent decision feedback equalizer. - K. Vijetha; B. Rajendra Naik (Int. J. Speech Technol., 2020)

FPGA implementation of polar codes for 5G eMBB control channels. - G. Aparna; Raparla Swathi; M. Kezia Joseph; C. N. Sujatha; B. Rajendra Naik (Int. J. Ultra Wideband Commun. Syst., 2021)

Proffering Secure Energy Aware Network-On-Chip (Noc) Using Incremental Cryptogine. - Sangeeta Singh; J. V. R. Ravindra; B. Rajendra Naik (Sustain. Comput. Informatics Syst., 2022)

Low power low area VLSI implementation of adaptive FIR filter using DA for decision feed back equalizer. - K. Vijetha; B. Rajendra Naik (Microprocess. Microsystems, 2022)

Improvement in the Quality of Services in Sub-6 GHz/mm Wave Using Equalizers and Decoupling of UL and DL with Machine Learning Approach. - R. Padmasree; B. Rajendra Naik (J. Commun., 2023)

A Read Delay Compensated and Write Assist SRAM Cell with Power Gated and Power Delay Product Reduction Circuitry. - Mucherla Usha Rani; N. Siva Sankara Reddy; B. Rajendra Naik (J. Circuits Syst. Comput., 2025)