Bob Rau

Affiliations:
  • Hewlett-Packard Labs, Palo Alto, CA, USA
  • ESL Inc., San Jose, CA, USA
  • Cydrome Inc., Los Gatos, CA, USA
  • Colorado State University, Computer Science Department, Fort Collins, CO, USA
  • University of Illinois at Urbana-Champaign, Coordinated Science Laboratory, IL, USA
  • Stanford University, CA, USA (PhD)


According to our database1, Bob Rau authored at least 44 papers between 1976 and 2002.

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Bibliography

2002
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators.
J. VLSI Signal Process., 2002

Constructing and exploiting linear schedules with prescribed parallelism.
ACM Trans. Design Autom. Electr. Syst., 2002

PICO: Automatically Designing Custom Computers.
Computer, 2002

2001
Compiling for EPIC architectures.
Proc. IEEE, 2001

Embedded Computer Architecture and Automation.
Computer, 2001

2000
Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats.
ACM Trans. Design Autom. Electr. Syst., 2000

EPIC: Explicititly Parallel Instruction Computing.
Computer, 2000

A Constructive Solution to the Juggling Problem in Processor Array Synthesis.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

Embedded Computing: New Directions in Architecture and Automation.
Proceedings of the High Performance Computing, 2000

The era of embedded computing.
Proceedings of the 2000 International Conference on Compilers, 2000

Efficient design space exploration in PICO.
Proceedings of the 2000 International Conference on Compilers, 2000

High-Level Synthesis of Nonprogrammable Hardware Accelerators.
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1999
Machine-Description Driven Compilers for EPIC and VLIW Processors.
Des. Autom. Embed. Syst., 1999

Automatic Architectural Synthesis of VLIW and EPIC Processors.
Proceedings of the 12th International Symposium on System Synthesis, 1999

1998
Optimization of Machine Descriptions for Efficient Use.
Int. J. Parallel Program., 1998

1997
Region-based compilation: Introduction, motivation, and initial experience.
Int. J. Parallel Program., 1997

1996
Iterative Modulo Scheduling.
Int. J. Parallel Program., 1996

Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks.
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

1995
Region-based compilation: an introduction and motivation.
Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

1994
Iterative modulo scheduling: an algorithm for software pipelining loops.
Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30, 1994

1993
Sentinel Scheduling for VLIW and Superscalar Processors.
ACM Trans. Comput. Syst., 1993

Instruction-level parallel processing: History, overview, and perspective.
J. Supercomput., 1993

Guest editors' introduction.
J. Supercomput., 1993

Reverse If-Conversion.
Proceedings of the ACM SIGPLAN'93 Conference on Programming Language Design and Implementation (PLDI), 1993

Dynamically scheduled VLIW processors.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

Predictability of load/store instruction latencies.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

1992
Register Allocation for Software Pipelined Loops.
Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation (PLDI), 1992

Code generation schema for modulo scheduled loops.
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

Sentinel Scheduling for VLIW and Superscalar Processors.
Proceedings of the ASPLOS-V Proceedings, 1992

1991
Data Flow and Dependence Analysis for Instruction Level Parallelism.
Proceedings of the Languages and Compilers for Parallel Computing, 1991

Pseudo-Randomly Interleaved Memory.
Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991

1989
Appucations Development On the Very Long Instruction Word Cydra-5.
Int. J. High Perform. Comput. Appl., 1989

The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-offs.
Computer, 1989

The Cydram 5 Stride-Insensitive Memory System.
Proceedings of the International Conference on Parallel Processing, 1989

1988
Cydra 5 Directed Dataflow Architecture.
Proceedings of the COMPCON'88, Digest of Papers, Thirty-Third IEEE Computer Society International Conference, San Francisco, California, USA, February 29, 1988

1982
Efficient code generation for horizontal architectures: Compiler techniques and architectural support.
Proceedings of the 9th International Symposium on Computer Architecture (ISCA 1982), 1982

Architectural Support for the Efficient Generation of Code for Horizontal Architectures.
Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, 1982

Systematically derived instruction sets for high-level language support.
Proceedings of the 20th Annual Southeast Regional Conference, 1982

1981
Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing.
Proceedings of the 14th annual workshop on Microprogramming, 1981

1979
Program Behavior and the Performance of Interleaved Memories.
IEEE Trans. Computers, 1979

Interleaved Memory Bandwidth in a Model of a Muyltiprocessor Computer System.
IEEE Trans. Computers, 1979

1978
Levels of representation of programs and the architecture of universal host machines.
Proceedings of the 11th annual workshop on Microprogramming, 1978

1977
The Effect of Instruction Fetch Strategies upon the Performance of Pipelined Instruction Units.
Proceedings of the 4th Annual Symposium on Computer Architecture, 1977

1976
A new philosophy for interconnection on multilayer boards.
Proceedings of the 13th Design Automation Conference, 1976


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