FAssem: FPGA Based Acceleration of De Novo Genome Assembly. - B. Sharat Chandra Varma 001; Kolin Paul; M. Balakrishnan; Dominique Lavenier (FCCM, 2013)

Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs. - B. Sharat Chandra Varma 001; Kolin Paul; M. Balakrishnan (VLSI Design, 2013)

High Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs. - B. Sharat Chandra Varma 001; Kolin Paul; M. Balakrishnan (DSD, 2014)

Accelerating Genome Assembly Using Hard Embedded Blocks in FPGAs. - B. Sharat Chandra Varma 001; Kolin Paul; M. Balakrishnan (VLSID, 2014)

Architecture for Dual-Mode Quadruple Precision Floating Point Adder. - Manish Kumar Jaiswal; B. Sharat Chandra Varma 001; Hayden Kwok-Hay So (ISVLSI, 2015)

Configurable Architectures for Multi-Mode Floating Point Adders. - Manish Kumar Jaiswal; B. Sharat Chandra Varma 001; Hayden Kwok-Hay So; M. Balakrishnan; Kolin Paul; Ray C. C. Cheung (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA. - Maolin Wang 002; Ho-Cheung Ng; Bob M. F. Chung; B. Sharat Chandra Varma 001; Manish Kumar Jaiswal; Kevin K. Tsia; Ho Cheung Shum; Hayden Kwok-Hay So (FPT, 2016)

High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform. - Ho-Cheung Ng; Maolin Wang 002; Bob M. F. Chung; B. Sharat Chandra Varma 001; Manish Kumar Jaiswal; Sam M. H. Ho; Kevin K. Tsia; Ho Cheung Shum; Hayden Kwok-Hay So (ReConFig, 2016)

Hardware acceleration of de novo genome assembly. - B. Sharat Chandra Varma 001; Kolin Paul; M. Balakrishnan; Dominique Lavenier (Int. J. Embed. Syst., 2017)

The VINEYARD integrated framework for hardware accelerators in the cloud. - Christoforos Kachris; Dimitrios Soudris; Stelios Mavridis; Manolis Pavlidakis; Christi Symeonidou; Christos Kozanitis; Angelos Bilas; Damon Fenacci; Sharatchandra Varma Bogaraju; Hans Vandierendonck; Dimitrios S. Nikolopoulos (SAMOS, 2018)

A Quantitative Study of Locality in GPU Caches for Memory-Divergent Workloads. - Sohan Lal; Sharatchandra Varma Bogaraju; Ben H. H. Juurlink (Int. J. Parallel Program., 2022)

Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network. - Maolin Wang 002; Kelvin C. M. Lee; Bob M. F. Chung; Sharatchandra Varma Bogaraju; Ho-Cheung Ng; Justin S. J. Wong; Ho Cheung Shum; Kevin K. Tsia; Hayden Kwok-Hay So (IEEE Trans. Neural Networks Learn. Syst., 2022)

An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite Imagery. - Cornell Castelino; Shashwat Khandelwal; Shanker Shreejith; Sharatchandra Varma Bogaraju (DSD, 2024)