B. Sharat Chandra Varma

According to our database, B. Sharat Chandra Varma authored at least 12 papers between 2013 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network.

Maolin Wang, Kelvin C. M. Lee, Bob M. F. Chung, Sharatchandra Varma Bogaraju, Ho-Cheung Ng, Justin S. J. Wong, Ho Cheung Shum, Kevin K. Tsia, Hayden Kwok-Hay So

IEEE Trans. Neural Networks Learn. Syst., 2022

A Quantitative Study of Locality in GPU Caches for Memory-Divergent Workloads.

Sohan Lal, Sharatchandra Varma Bogaraju, Ben H. H. Juurlink

Int. J. Parallel Program., 2022

2018

The VINEYARD integrated framework for hardware accelerators in the cloud.

Christoforos Kachris, Dimitrios Soudris, Stelios Mavridis, Manolis Pavlidakis, Christi Symeonidou, Christos Kozanitis, Angelos Bilas, Damon Fenacci, Sharatchandra Varma Bogaraju, Hans Vandierendonck, Dimitrios S. Nikolopoulos

Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

2017

Hardware acceleration of de novo genome assembly.

B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier

Int. J. Embed. Syst., 2017

2016

High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform.

Ho-Cheung Ng, Maolin Wang, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Sam M. H. Ho, Kevin K. Tsia, Ho Cheung Shum, Hayden Kwok-Hay So

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA.

Maolin Wang, Ho-Cheung Ng, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Kevin K. Tsia, Ho Cheung Shum, Hayden Kwok-Hay So

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2015

Configurable Architectures for Multi-Mode Floating Point Adders.

Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So, M. Balakrishnan, Kolin Paul, Ray C. C. Cheung

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Architecture for Dual-Mode Quadruple Precision Floating Point Adder.

Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014

Accelerating Genome Assembly Using Hard Embedded Blocks in FPGAs.

B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

High Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs.

B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013

Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs.

B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

FAssem: FPGA Based Acceleration of De Novo Genome Assembly.

B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013