A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies. - B. Srinivasu; K. Sridharan 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

CoLPUF : A Novel Configurable LFSR-based PUF. - B. Srinivasu; Vikramkumar Pudi; Anupam Chattopadhyay; Kwok-Yan Lam (APCCAS, 2018)

High Performance Ternary Full Adder in CNFET-Memristor Logic Technology. - Panasa Srikanth; B. Srinivasu (VDAT, 2022)

Memristor-based High Speed and Area Efficient Comparators in IMPLY Logic. - Nandit Kaushik; B. Srinivasu (VLSID, 2023)

Approximate Ternary Matrix Multiplication for Image Processing and Neural Networks. - L. Hemanth Krishna; B. Srinivasu (ISVLSI, 2024)

Energy Efficient Memristor-Based Subtractors and Comparator for In-Memory Computing in MAGIC. - Nandit Kaushik; B. Srinivasu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

MAGIC-Based High-Speed Adders for in-Memory Computing Using Memristors. - Shri Janani Senthil; B. Srinivasu (VLSID, 2025)

Advancing Neural Network Performance with Probabilistic Computing for ReLU Function. - Amit Singh; Amit Kumar Jangid; B. Srinivasu (VLSID, 2025)