Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction. - B. Suresh; Biswadeep Chaterjee; R. Harinath (VLSI Design, 2000)

Object Oriented Parallel Programming Model on a Network of Workstations. - B. Suresh; R. Nadarajan (International Conference on Computational Science, 2003)

Application of Alpha Power Law Models to PLL Design Methodology. - B. Suresh; V. Visvanathan; R. S. Krishnan; H. S. Jamadagni (VLSI Design, 2005)

Detection of splicing forgery using differential evolution and wavelet decomposition. - Abhishek Kashyap; B. Suresh; Hariom Gupta (Comput. J., 2020)

Machine Learning-based Oddity Detection of Smoke and Gas Sensor Data in a Large Gated Community. - D. Sri Harsha; B. Suresh; K. L. V. Sai Prakash Sakuru (iSES, 2022)

Robust Detection of Copy-Move Forgery Based on Wavelet Decomposition and Firefly Algorithm. - Abhishek Kashyap; B. Suresh; Hariom Gupta (Comput. J., 2022)

Performance Evaluation of Supervisory Machine Learning Algorithms for Cellular Networks Payload Enhancement in Downlink. - B. Suresh; K. L. V. Sai Prakash Sakuru (ICCCNT, 2023)