A Reliability Level List based SDD Algorithm for Binary Cyclic Block Codes. - B. Yamuna; T. R. Padmanabhan (Int. J. Comput. Commun. Control, 2012)

A minimal search soft decision list decoding algorithm for Reed-Solomon codes. - B. Yamuna; T. R. Padmanabhan (Int. J. Inf. Commun. Technol., 2014)

Reliability level list-based decoding of multilevel modulated block codes. - B. Yamuna; T. R. Padmanabhan (Int. J. Inf. Commun. Technol., 2016)

A low complex turbo decoding algorithm with early iteration termination. - C. R. Seethal; B. Yamuna (ICACCI, 2017)

FPGA Implementation of an Efficient High Speed Max-log-MAP Decoder. - Aishwarya Ambat; Karthi Balasubramanian; B. Yamuna; Deepak Mishra (ICACCI, 2018)

Low Power and Area Efficient Max-log -MAP Decoder. - Kalpana Eluri; B. Yamuna; Karthi Balasubramanian; Deepak Mishra (ICACCI, 2018)

Effect of hardware Trojans on the performance of a coded communication system. - A. R. Aravind; S. R. Kesavaraman; Karthi Balasubramanian; B. Yamuna; Karthikeyan Lingasubramanian (ICCE, 2018)

Effect of sign-bit-flipping trojan on turbo coded communication systems. - Karthi Balasubramanian; B. Yamuna; Salija P; Karthikeyan Lingasubramanian; Deepak Mishra (ICDCN, 2019)

A novel reliability-based high performance decoding algorithm for short block length turbo codes. - Salija P; B. Yamuna; T. R. Padmanabhan; Deepak Mishra (Int. J. Ad Hoc Ubiquitous Comput., 2020)

A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study. - Varsha Kakkara; Karthi Balasubramanian; B. Yamuna; Deepak Mishra; Karthikeyan Lingasubramanian; Senthil Murugan (PeerJ Comput. Sci., 2020)

A Generic Reliability Based Direct Decoding Algorithm for Turbo Codes. - Salija P; B. Yamuna; T. R. Padmanabhan; Deepak Mishra (Wirel. Pers. Commun., 2022)

Scalable FPGA Implementation of a Reliability-Based Direct Turbo Decoder for Short Block Codes. - Senthil Murugan; Ramesh Bhakthavatchalu; Karthi Balasubramanian; B. Yamuna; Deepak Mishra; Sree Ranjani Rajendran (IEEE Access, 2025)