A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS. - Jong-In Kim; Ba-Ro-Saim Sung; Wan Kim; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2013)

26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS. - Ba-Ro-Saim Sung; Dong-Shin Jo; Il-Hoon Jang; Dong-Suk Lee; Yong-Sang You; Yong-Hee Lee; Ho-Jin Park; Seung-Tak Ryu (ISSCC, 2015)

A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation. - Jong-In Kim; Dong-Ryeol Oh; Dong-Shin Jo; Ba-Ro-Saim Sung; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2015)

A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm2. - Si-Nai Kim; Mee-Ran Kim; Ba-Ro-Saim Sung; Hyun-Wook Kang; Min-Hyung Cho; Seung-Tak Ryu (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration. - Dong-Shin Jo; Ba-Ro-Saim Sung; Min-Jae Seo; Woo-Cheol Kim; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2020)