A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology. - Mohammed Iftekhar; Harshan Gowda; Pascal Kneuper; Babak Sadiye; Wolfgang Mueller; Johann-Christoph Scheytt (BCICTS, 2023)

Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture. - Lars Luchterhandt; Tom Nellius; Robert Beck; Rainer Dömer; Pascal Kneuper; Wolfgang Mueller; Babak Sadiye (MBMV, 2023)

A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing. - Paul Palomero Bernardo; Patrick Schmid; Oliver Bringmann 001; Mohammed Iftekhar; Babak Sadiye; Wolfgang Mueller; Andreas Koch 001; Eyck Jentzsch; Axel Sauer; Ingo Feldner; Wolfgang Ecker (DATE, 2024)