Continuous-time linear equalizer with automatic boosting gain adaptation and input offset cancellation. - Baek-Jin Lim; Changsik Yoo (Int. J. Circuit Theory Appl., 2018)

A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics. - Hojun Yoon; Wonjoo Jung; Jaewoo Park; Jindo Byun; Hyungmin Jin; Hyunyoon Cho; Youngmin Kim; Baek-Jin Lim; Young-Chul Cho; Youngdon Choi; Jung-Hwan Choi; Hyungjong Ko; et al. (ESSCIRC, 2021)

A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend. - Hyeongmin Seo; Jiyun Han; Kyungmin Kim 003; Baek-Jin Lim; EunSeok Shin; Youngdon Choi; Hyungjong Ko; Jung-Hwan Choi; Sang-Hyun Lee; Changsik Yoo; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2023)