22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme. - Chi-Sung Oh; Ki Chul Chun; Young-Yong Byun; Yong-Ki Kim; So-Young Kim; Yesin Ryu; Jaewon Park; Sinho Kim; Sang-uhn Cha; Dong-Hak Shin; Jungyu Lee 002; Jong-Pil Son; et al. (ISSCC, 2020)

A 2.4-to-4.2GHz 440.2fsrms-Integrated-Jitter 4.3mW Ring-Oscillator-Based PLL Using a Switched-Capacitor-Bias-Based Sampling PD in 4nm FinFET CMOS. - Jaehong Jung; Kyungmin Lee; Gunwoo Kong; Baekmin Lim; Seungjin Kim; Seunghyun Oh; Jongwoo Lee (VLSI Technology and Circuits, 2023)

A 2.8-to-7.2GT/s DDR5 Registering Clock Driver IC with Parallel-Data Timing and Pin-to-Pin Skew Calibration for a Dual In-Line Memory Module. - Joomyoung Kim; Jaehong Jung; Kwangmin Lim; Barosaim Sung; Jaekwon Kim; Baekmin Lim; Tae-Gun Noh; Jaehoon Lee 005; Hyun-Gi Seok; Youngsea Cho; Gyusik Kim; Takahiro Nomiyama; et al. (A-SSCC, 2024)