Solving four-colouring map problem using genetic algorithm. - Bah-Hwee Gwee; Meng-Hiot Lim; Jiun-Sien Ho (ANNES, 1993)

Intelligent monitoring of a frequency-trimming process. - M. H. Lim; Bah-Hwee Gwee; Y. Kawada (J. Intell. Manuf., 1993)

Polyominoes tiling by a genetic algorithm. - Bah-Hwee Gwee; M. H. Lim (Comput. Optim. Appl., 1996)

A GA paradigm for learning fuzzy rules. - M. H. Lim; Susanto Rahardja; Bah-Hwee Gwee (Fuzzy Sets Syst., 1996)

An investigation on the parameters affecting total harmonic distortion in class D amplifiers. - Meng Tong Tan; Hock-Chuan Chua; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2000)

A GA with heuristic-based decoder for IC floorplanning. - Bah-Hwee Gwee; Meng-Hiot Lim (Integr., 2000)

A novel low-power low-voltage Class D amplifier with feedback for improving THD, power efficiency and gain linearity. - Joseph Sylvester Chang; Bah-Hwee Gwee; Yong Seng Lon; Meng Tong Tan (ISCAS (1), 2001)

A digital Class D amplifier design embodying a novel sampling process and pulse generator. - Huiyun Li; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS (4), 2001)

Low-voltage micropower asynchronous multiplier for hearing instruments. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS (1), 2002)

Low-voltage asynchronous adders for low power and high speed applications. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS (1), 2002)

A Hybrid Genetic Hill-climbing Algorithm for Four-Coloring Map Problems. - Bah-Hwee Gwee; Joseph Sylvester Chang (HIS, 2003)

A low-voltage micropower asynchronous multiplier for a multiplierless FIR filter. - Chien-Chung Chua; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS (5), 2003)

A novel sampling process and pulse generator for a low distortion digital pulse-width modulator for digital class D amplifiers. - Bah-Hwee Gwee; Joseph Sylvester Chang; Victor Adrian; H. Amir (ISCAS (4), 2003)

A Low Voltage Micropower 16-Word by 16-Bit 3-Port Asynchronous Register File. - Khia-Ho Chang; Bah-Hwee Gwee; Joseph Sylvester Chang (VLSI, 2003)

A novel combined first and second order Lagrange interpolation sampling process for a digital class D amplifier. - Victor Adrian; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS (3), 2004)

A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS (2), 2004)

A combined interpolatorless interpolation and high accuracy sampling process for digital class D amplifiers. - Victor Adrian; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS (6), 2005)

Low-voltage micropower multipliers with reduced spurious switching. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS (4), 2005)

An evolution search algorithm for solving N-queen problems. - Bah-Hwee Gwee; Meng-Hiot Lim (Int. J. Comput. Appl. Technol., 2005)

A micropower low-distortion digital class-D amplifier based on an algorithmic pulsewidth modulator. - Bah-Hwee Gwee; Joseph Sylvester Chang; Victor Adrian (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A micropower low-voltage multiplier with reduced spurious switching. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Optimized Algorithm for Computing Invariants of Ordinary Petri Nets. - Chong-Fatt Law; Bah-Hwee Gwee; Joseph S. Chang (ACIS-ICIS, 2006)

An acoustic noise suppression system with reduced musical artifacts. - Victor Adrian; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS, 2006)

A low-energy low-voltage asynchronous 8051 microcontroller core. - Kok-Leong Chang; Bah-Hwee Gwee (ISCAS, 2006)

A 16-Channel Low-Power Nonuniform Spaced Filter Bank Core for Digital Hearing Aids. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

An Asynchronous Dual-Rail Multiplier based on Energy-Efficient STFB Templates. - Kok-Leong Chang; Bah-Hwee Gwee; Yuanjin Zheng (ISCAS, 2007)

A Low Energy FFT/IFFT Processor for Hearing Aids. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS, 2007)

A 32-point FFT based Noise Reduction Algorithm for Single Channel Speech Signals. - Kunal Mukherjee; Bah-Hwee Gwee (ISCAS, 2007)

Design of several asynchronous-logic macrocells for a low-voltage micropower cell library. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (IET Circuits Devices Syst., 2007)

Low energy 16-bit Booth leapfrog array multiplier using dynamic adders. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (IET Circuits Devices Syst., 2007)

Fast and memory-efficient invariant computation of ordinary Petri nets. - Chong-Fatt Law; Bah-Hwee Gwee; Joseph Sylvester Chang (IET Comput. Digit. Tech., 2007)

Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (IEEE J. Solid State Circuits, 2007)

A semi-custom memory design for an asynchronous 8051 microcontroller. - Kok-Leong Chang; Bah-Hwee Gwee; Yuanjin Zheng (ISCAS, 2008)

De-synchronization of a point-of-sales digital-logic controller. - Kok-Leong Chang; Yao Zhu; Bah-Hwee Gwee (ISCAS, 2008)

Asynchronous Control Network Optimization Using Fast Minimum-Cycle-Time Analysis. - Chong-Fatt Law; Bah-Hwee Gwee; Joseph Sylvester Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A Performance Comparison on Asynchronous Matched-delay Templates. - Kok-Leong Chang; Bah-Hwee Gwee; Yuanjin Zheng (ISCAS, 2009)

Fine-grained Power Gating for Leakage and Short-circuit Power Reduction by using Asynchronous-logic. - Tong Lin 001; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS, 2009)

A Low-Voltage Micropower Digital Class-D Amplifier Modulator for Hearing Aids. - Victor Adrian; Joseph S. Chang; Bah-Hwee Gwee (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A Low-Voltage Micropower Asynchronous Multiplier With Shift-Add Multiplication Approach. - Bah-Hwee Gwee; Joseph S. Chang; Yiqiong Shi; Chien-Chung Chua; Kwen-Siong Chong (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A highly efficient method for extracting FSMs from flattened gate-level netlist. - Yiqiong Shi; Chan Wai Ting; Bah-Hwee Gwee; Ye Ren (ISCAS, 2010)

A Randomized Wrapped-Around Pulse Position Modulation Scheme for DC-DC Converters. - Victor Adrian; Joseph S. Chang; Bah-Hwee Gwee (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A low-power dual-rail inputs write method for bit-interleaved memory cells. - Junchao Chen; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS, 2011)

Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation. - Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang; Yin Sun; Kok-Leong Chang (ISCAS, 2011)

Asynchronous DSP for low-power energy-efficient embedded systems. - Yiqiong Shi; Bah-Hwee Gwee; Joseph Sylvester Chang (Microprocess. Microsystems, 2011)

Modeling and Synthesis of Asynchronous Pipelines. - Chong-Fatt Law; Bah-Hwee Gwee; Joseph Sylvester Chang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A comparative study on asynchronous Quasi-Delay-Insensitive templates. - Kok-Leong Chang; Tong Lin 001; Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2012)

An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability. - Junchao Chen; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2012)

Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. - Weng-Geng Ho; Kwen-Siong Chong; Tong Lin 001; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2012)

Extracting functional modules from flattened gate-level netlist. - Yiqiong Shi; Bah-Hwee Gwee; Ye Ren; Thet Khaing Phone; Chan Wai Ting (ISCIT, 2012)

Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors. - Kwen-Siong Chong; Kok-Leong Chang; Bah-Hwee Gwee; Joseph S. Chang (IEEE J. Solid State Circuits, 2012)

A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic. - Kok-Leong Chang; Tong Lin 001; Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2013)

Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU. - Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2013)

Designing globally-asynchronous-locally-system from multi-rate Simulink model. - Yiqiong Shi; Bah-Hwee Gwee (NEWCAS, 2013)

Synchronous-Logic and Asynchronous-Logic 8051 Microcontroller Cores for Realizing the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects. - Kok-Leong Chang; Joseph S. Chang; Bah-Hwee Gwee; Kwen-Siong Chong (IEEE J. Emerg. Sel. Topics Circuits Syst., 2013)

An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive VDD System for Wireless Sensor Networks. - Tong Lin 001; Kwen-Siong Chong; Joseph S. Chang; Bah-Hwee Gwee (IEEE J. Solid State Circuits, 2013)

Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips. - Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (APCCAS, 2014)

A Randomized Modulation scheme for filterless digital Class D audio amplifiers. - Victor Adrian; Cui Keer; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS, 2014)

Synthesis of asynchronous QDI circuits using synchronous coding specifications. - Rong Zhou; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang; Weng-Geng Ho (ISCAS, 2014)

A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation. - Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang; Ne Kyaw Zwa Lwin (ISIC, 2014)

A self-oscillating class D audio amplifier with dual voltage and current feedback. - Salma Nashit; Victor Adrian; Cui Keer; Quoc-An Mai; Bah-Hwee Gwee; Joseph S. Chang (ISIC, 2014)

Design of an output stage for high switching frequency DC-DC converters. - Tian-Shun Ng; Yin Sun; Victor Adrian; Bah-Hwee Gwee; Joseph S. Chang (ISIC, 2014)

Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing. - Junchao Chen; Kwen-Siong Chong; Bah-Hwee Gwee (Circuits Syst. Signal Process., 2014)

A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA). - Rong Zhou; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC). - Weng-Geng Ho; Kwen-Siong Chong; Ne Kyaw Zwa Lwin; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2015)

Novel real-time system design for floating-point sub-Nyquist multi-coset signal blind reconstruction. - Hongxu Yin; Bah-Hwee Gwee; Zhiping Lin 001; Achanna Anil Kumar; Sirajudeen Gulam Razul; Chong Meng Samson See (ISCAS, 2015)

A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline. - Rong Zhou; Kwen-Siong Chong; Tong Lin 001; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2015)

Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer. - Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (IET Circuits Devices Syst., 2015)

Interceptive side channel attack on AES-128 wireless communications for IoT applications. - Ali Akbar Pammu; Kwen-Siong Chong; Weng-Geng Ho; Bah-Hwee Gwee (APCCAS, 2016)

Success rate model for fully AES-128 in correlation power analysis. - Ali Akbar Pammu; Kwen-Siong Chong; Ne Kyaw Zwa Lwin; Weng-Geng Ho; Nan Liu 002; Bah-Hwee Gwee (APCCAS, 2016)

Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications. - Nan Liu 002; Kwen-Siong Chong; Weng-Geng Ho; Bah-Hwee Gwee; Joseph Sylvester Chang (DATE, 2016)

High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits. - Weng-Geng Ho; Nan Liu 002; Kyaw Zwa Lwin Ne; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS, 2016)

Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM. - Weng-Geng Ho; Kyaw Zwa Lwin Ne; N. Prashanth Srinivas; Kwen-Siong Chong; Tony Tae-Hyoung Kim; Bah-Hwee Gwee (ISCAS, 2016)

Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack. - Weng-Geng Ho; Ali Akbar Pammu; Nan Liu 002; Kyaw Zwa Lwin Ne; Kwen-Siong Chong; Bah-Hwee Gwee (ISIC, 2016)

A high-efficiency Class-E polar power-amplifier with a novel digitally-controlled output matching network. - Qianqian Liu; Victor Adrian; Bah-Hwee Gwee; Joseph S. Chang (ISIC, 2016)

Highly secured arithmetic hiding based S-Box on AES-128 implementation. - Ali Akbar Pammu; Kwen-Siong Chong; Bah-Hwee Gwee (ISIC, 2016)

Secured Low Power Overhead Compensator Look-Up-Table (LUT) Substitution Box (S-Box) Architecture. - Ali Akbar Pammu; Kwen-Siong Chong; Bah-Hwee Gwee (NAS, 2016)

DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer. - James Lim; Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee (ISCAS, 2017)

A class-E RF power amplifier with a novel matching network for high-efficiency dynamic load modulation. - Qianqian Liu; Victor Adrian; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2017)

Highly secured state-shift local clock circuit to countermeasure against side channel attack. - Ali Akbar Pammu; Kwen-Siong Chong; Bah-Hwee Gwee (ISCAS, 2017)

A low-harmonics low-noise randomized modulation scheme for multi-phase DC-DC converters. - Cui Keer; Victor Adrian; Yin Sun; Bah-Hwee Gwee; Joseph S. Chang (NEWCAS, 2017)

Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template. - Kwen-Siong Chong; Weng-Geng Ho; Tong Lin 001; Bah-Hwee Gwee; Joseph S. Chang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Comparative Analysis of 65nm CMOS SRAM and Commercial SRAMs in Security Vulnerability Evaluation. - Weng-Geng Ho; Zixian Zheng; Kwen-Siong Chong; Bah-Hwee Gwee (DSP, 2018)

Deep Learning for Automatic IC Image Analysis. - Xuenong Hong; Deruo Cheng; Yiqiong Shi; Tong Lin 001; Bah-Hwee Gwee (DSP, 2018)

Hybrid K-Means Clustering and Support Vector Machine Method for via and Metal Line Detections in Delayered IC Images. - Deruo Cheng; Yiqiong Shi; Tong Lin 001; Bah-Hwee Gwee; Kar-Ann Toh (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Noise-Shaped Randomized Modulation for Switched-Mode DC-DC Converters. - Cui Keer; Victor Adrian; Bah-Hwee Gwee; Joseph S. Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design. - Weng-Geng Ho; Kwen-Siong Chong; Kyaw Zwa Lwin Ne; Bah-Hwee Gwee; Joseph S. Chang (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells. - Kwen-Siong Chong; Aparna Shreedhar; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Weng-Geng Ho; Chao Wang 096; Jun Zhou 017; Bah-Hwee Gwee; Joseph S. Chang (AsianHOST, 2019)

Global Template Projection and Matching Method for Training-Free Analysis of Delayered IC Images. - Deruo Cheng; Yiqiong Shi; Tong Lin 001; Bah-Hwee Gwee; Kar-Ann Toh (ISCAS, 2019)

Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design. - Aparna Shreedhar; Kwen-Siong Chong; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; L. Nalangilli; Wei Shu; Joseph S. Chang; Bah-Hwee Gwee (ISCAS, 2019)

Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications. - Weng-Geng Ho; Ali Akbar Pammu; Kyaw Zwa Lwin Ne; Kwen-Siong Chong; Bah-Hwee Gwee (SoCC, 2019)

A Hierarchical Multiclassifier System for Automated Analysis of Delayered IC Images. - Deruo Cheng; Yiqiong Shi; Bah-Hwee Gwee; Kar-Ann Toh; Tong Lin 001 (IEEE Intell. Syst., 2019)

A Secure Data-Toggling SRAM for Confidential Data Protection. - Weng-Geng Ho; Kwen-Siong Chong; Tony Tae-Hyoung Kim; Bah-Hwee Gwee (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Highly Efficient Side Channel Attack with Profiling through Relevance-Learning on Physical Leakage Information. - Ali Akbar Pammu; Kwen-Siong Chong; Yi Wang 016; Bah-Hwee Gwee (IEEE Trans. Dependable Secur. Comput., 2019)

A High Throughput and Secure Authentication-Encryption AES-CCM Algorithm on Asynchronous Multicore Processor. - Ali Akbar Pammu; Weng-Geng Ho; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Bah-Hwee Gwee (IEEE Trans. Inf. Forensics Secur., 2019)

Hardware Attack and Assurance with Machine Learning: A Security Threat to Circuits and Systems. - Bah-Hwee Gwee (APCCAS, 2020)

High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC. - Weng-Geng Ho; Chuan-Seng Ng; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Bah-Hwee Gwee (APCCAS, 2020)

A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications. - Weng-Geng Ho; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Jun-Sheng Ng; Juncheng Chen; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2020)

A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES). - Jun-Sheng Ng; Juncheng Chen; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee (ISCAS, 2020)

High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications. - Weng-Geng Ho; Ali Akbar Pammu; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Bah-Hwee Gwee (ISOCC, 2020)

Joint Anomaly Detection and Inpainting for Microscopy Images Via Deep Self-Supervised Learning. - Ling Huang; Deruo Cheng; Xulei Yang; Tong Lin 001; Yiqiong Shi; Kaiyi Yang; Bah-Hwee Gwee; Bihan Wen (ICIP, 2021)

Normalized Differential Power Analysis - for Ghost Peaks Mitigation. - Juncheng Chen; Jun-Sheng Ng; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Weng-Geng Ho; Kwen-Siong Chong; Zhiping Lin 001; Joseph Sylvester Chang; Bah-Hwee Gwee (ISCAS, 2021)

Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation. - Kwen-Siong Chong; Jun-Sheng Ng; Juncheng Chen; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Weng-Geng Ho; Joseph Sylvester Chang; Bah-Hwee Gwee (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection. - Weng-Geng Ho; Kwen-Siong Chong; Tony Tae-Hyoung Kim; Bah-Hwee Gwee (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Novel Normalized Variance-Based Differential Power Analysis Against Masking Countermeasures. - Juncheng Chen; Jun-Sheng Ng; Kwen-Siong Chong; Zhiping Lin 001; Bah-Hwee Gwee (IEEE Trans. Inf. Forensics Secur., 2021)

Incremental Linear Regression Attack. - Juncheng Chen; Jun-Sheng Ng; Nay Aung Kyaw; Zhili Zou; Kwen-Siong Chong; Zhiping Lin 001; Bah-Hwee Gwee (AsianHOST, 2022)

Non-profiling based Correlation Optimization Deep Learning Analysis. - Juncheng Chen; Jun-Sheng Ng; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Zhiping Lin 001; Joseph Sylvester Chang; Bah-Hwee Gwee (ISCAS, 2022)

An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations. - Jun-Sheng Ng; Juncheng Chen; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Joseph S. Chang; Bah-Hwee Gwee (ISCAS, 2022)

A Versatile and Accurate Vector-Based Method for Modeling and Analyzing Planar Air-Core Inductors. - Sun-Yang Tay; Victor Adrian; Joseph S. Chang; Jinhen Lee; Bah-Hwee Gwee (ISCAS, 2022)

Unsupervised Domain Adaptation with Histogram-gated Image Translation for Delayered IC Image Analysis. - Yee-Yang Tee; Deruo Cheng; Chye-Soon Chee; Tong Lin 001; Yiqiong Shi; Bah-Hwee Gwee (CoRR, 2022)

Delayered IC image analysis with template-based Tanimoto Convolution and Morphological Decision. - Deruo Cheng; Yiqiong Shi; Tong Lin 001; Bah-Hwee Gwee; Kar-Ann Toh (IET Circuits Devices Syst., 2022)

A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks. - Jun-Sheng Ng; Juncheng Chen; Kwen-Siong Chong; Joseph S. Chang; Bah-Hwee Gwee (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Deep-learning-based X-ray CT Slice Analysis for Layout Verification in Printed Circuit Boards. - Deruo Cheng; Yiqiong Shi; Yee-Yang Tee; Jingsi Song; Xue Wang; Bihan Wen; Bah-Hwee Gwee (AICAS, 2023)

GRACER: Graph-Based Standard Cell Recognition in IC Images for Hardware Assurance. - Erdong Huang; Xuenong Hong; Tong Lin 001; Yiqiong Shi; Bah-Hwee Gwee (IECON, 2023)

SEM2GDS: A Deep-Learning Based Framework To Detect Malicious Modifications In IC Layout. - Tong Lin 001; Yiqiong Shi; Bah-Hwee Gwee (ISCAS, 2023)

Real-time Traffic Classification in Encrypted Wireless Communication Network. - Yongming Chen; Yuzhou Tong; Bah-Hwee Gwee; Qi Cao 002; Sirajudeen Gulam Razul; Zhiping Lin 001 (ISCAS, 2023)

A 3D-Printed Fourth-Order Stacked Filter for Integrated DC-DC Converters. - Jinhen Lee; Victor Adrian; Sun-Yang Tay; Yanshan Xie; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2023)

Improving FPGA-based Async-logic AES Accelerator with the Integration of Sync-logic Block RAMs. - Jun-Sheng Ng; Juncheng Chen; Si Wu; Nay Aung Kyaw; Kwen-Siong Chong; Zhiping Lin 001; Bah-Hwee Gwee (ISCAS, 2023)

A Residual-Remainder Coupled Unlimited Sampling Framework for High Dynamic Range Signal Conversion. - Zixiang Zhou; Lei Sun 006; Hangcheng Han; Juncheng Chen; Bah-Hwee Gwee; Zhiping Lin 001 (ISCAS, 2023)

Patch-Based Adversarial Training for Error-Aware Circuit Annotation of Delayered IC Images. - Yee-Yang Tee; Xuenong Hong; Deruo Cheng; Chye-Soon Chee; Yiqiong Shi; Tong Lin 001; Bah-Hwee Gwee (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

GraphClusNet: A Hierarchical Graph Neural Network for Recovered Circuit Netlist Partitioning. - Xuenong Hong; Tong Lin 001; Yiqiong Shi; Bah-Hwee Gwee (IEEE Trans. Artif. Intell., 2023)

A Novel Voltage-Controlled Oscillator Linearized by a Resistorless Dynamic-Degeneration Technique. - Jinhen Lee; Victor Adrian; Bah-Hwee Gwee; Joseph Sylvester Chang (APCCAS, 2024)

An Energy-Efficient and High-Accuracy Spiking Neural Network Utilizing Asynchronous CORDIC for On-FPGA STDP Learning. - Shirui Sheng; Kwen-Siong Chong; Jun-Sheng Ng; Zhiping Lin 001; Joseph S. Chang; Bah-Hwee Gwee (APCCAS, 2024)

A Novel Non-profiling Side-Channel Attack on Masked Devices with Connectivity Matrix. - Juncheng Chen; Han Zhang; Zishuo Yang; Yicheng Xu; Nay Aung Kyaw; Kwen-Siong Chong; Zhiping Lin 001; Bah-Hwee Gwee (ISCAS, 2024)

MLConnect: A Machine Learning Based Connection Prediction Framework for Error Correction in Recovered Circuit. - Xuenong Hong; Zilong Hu; Han Zhang; Yee-Yang Tee; Tong Lin 001; Yiqiong Shi; Deruo Cheng; Bah-Hwee Gwee (ISCAS, 2024)

A Method for Out-of-Distribution Detection in Encrypted Mobile Traffic Classification. - Yuzhou Tong; Yongming Chen; Bah-Hwee Gwee; Qi Cao 002; Sirajudeen Gulam Razul; Zhiping Lin 001 (ISCAS, 2024)

Unpaired Synthesis of IC Scanning Electron Microscopy Images with Structural Constraints. - Luyun Li; Deruo Cheng; Yiqiong Shi; Bah-Hwee Gwee (IST, 2024)

SAMIC: Segment Anything Model for Integrated Circuit Image Analysis. - Yong-Jian Ng; Yee-Yang Tee; Deruo Cheng; Bah-Hwee Gwee (TENCON, 2024)

Integrated Circuit Mask-Generative Adversarial Network for Circuit Annotation With Targeted Data Augmentation. - Yee-Yang Tee; Deruo Cheng; Yiqiong Shi; Tong Lin 001; Bah-Hwee Gwee (IEEE Intell. Syst., 2024)

Securing Against Side-Channel Attacks With Wide-Range In Situ Random Voltage Dithering on Async-Logic AES Engine. - Jun-Sheng Ng; Juncheng Chen; Nay Aung Kyaw; Kwen-Siong Chong; Bah-Hwee Gwee (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A Novel Energy-Efficient Continuous-Time Hysteretic VCO-Based Comparator. - Jinhen Lee; Victor Adrian; Kinglouis Steven Tantra; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2025)

Multiple Hypothesis Testing for SEM Image Processing: A Case Study on Standard Cell Partition. - Xiaoyu Ma; Yizhen Li; Feng Ji; Tong Lin 001; Yiqiong Shi; Deruo Cheng; Bah-Hwee Gwee (ISCAS, 2025)

SSRNet: Few-shot IC Segmentation in Automated PCB Image Processing. - Yuhang Wang; Xinrui Wang 004; Deruo Cheng; Tong Lin 001; Feng Ji; Yiqiong Shi; Bah-Hwee Gwee (ISCAS, 2025)

N-MUX: Neighborhood-Based Logic Locking Against Machine Learning Attacks. - Han Zhang; Xuenong Hong; Shirui Sheng; Juncheng Chen; Nay Aung Kyaw; Kwen-Siong Chong; Zhiping Lin 001; Bah-Hwee Gwee (ISCAS, 2025)

Live Demonstration: An Area and Energy Efficient Reconfigurable Cryptographic Accelerator Based SoC Design for Securing IoT Devices. - Xvpeng Zhang; Bingqiang Liu; Lingyun Hu; Zixuan Shen; Zaisheng He; Dengke Xu; Bah-Hwee Gwee; Chao Wang (ISCAS, 2025)

Long-Short-GNN: A Novel Graph Neural Network for Detecting FPGA IP Circuits for Hardware Assurance. - Heyi Zhang; Tong Lin 001; Feng Ji; Deruo Cheng; Yiqiong Shi; Bah-Hwee Gwee (ISCAS, 2025)

GNNReveal: A Novel Graph-Neural-Network-Based Attack Method for Integrated Circuit Logic Gate Decamouflaging. - Xuenong Hong; Yee-Yang Tee; Zilong Hu; Tong Lin 001; Yiqiong Shi; Deruo Cheng; Bah-Hwee Gwee (IEEE Intell. Syst., 2025)