Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube. - Ramyad Hadidi; Bahar Asgari; Burhan Ahmad Mudassar; Saibal Mukhopadhyay; Sudhakar Yalamanchili; Hyesoon Kim (IISWC, 2017)

Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology. - Ramin Rajaei; Bahar Asgari; Mahmoud Tabandeh; Mahdi Fazeli (Turkish J. Electr. Eng. Comput. Sci., 2017)

Micro-architectural approach to the efficient employment of STTRAM cells in a microprocessor register file. - Bahar Asgari; Mahdi Fazeli; Ahmad Patooghy; Seyed Vahid Azhari (IET Comput. Digit. Tech., 2017)

Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube. - Ramyad Hadidi; Bahar Asgari; Jeffrey S. Young 001; Burhan Ahmad Mudassar; Kartikay Garg; Tushar Krishna; Hyesoon Kim (ISPASS, 2018)

Memory Slices: A Modular Building Block for Scalable, Intelligent Memory Systems. - Bahar Asgari; Saibal Mukhopadhyay; Sudhakar Yalamanchili (CoRR, 2018)

LODESTAR: Creating Locally-Dense CNNs for Efficient Inference on Systolic Arrays. - Bahar Asgari; Ramyad Hadidi; Hyesoon Kim; Sudhakar Yalamanchili (DAC, 2019)

SuDoku: Tolerating High-Rate of Transient Failures for Enabling Scalable STTRAM. - Prashant J. Nair; Bahar Asgari; Moinuddin K. Qureshi (DSN, 2019)

Capella: Customizing Perception for Edge Devices by Efficiently Allocating FPGAs to DNNs. - Younmin Bae; Ramyad Hadidi; Bahar Asgari; Jiashen Cao; Hyesoon Kim (FPL, 2019)

Characterizing the Deployment of Deep Neural Networks on Commercial Edge Devices. - Ramyad Hadidi; Jiashen Cao; Yilun Xie; Bahar Asgari; Tushar Krishna; Hyesoon Kim (IISWC, 2019)

ERIDANUS: Efficiently Running Inference of DNNs Using Systolic Arrays. - Bahar Asgari; Ramyad Hadidi; Hyesoon Kim; Sudhakar Yalamanchili (IEEE Micro, 2019)

PISCES: Power-Aware Implementation of SLAM by Customizing Efficient Sparse Algebra. - Bahar Asgari; Ramyad Hadidi; Nima Shoghi Ghaleshahi; Hyesoon Kim (DAC, 2020)

ASCELLA: Accelerating Sparse Computation by Enabling Stream Accesses to Memory. - Bahar Asgari; Ramyad Hadidi; Hyesoon Kim (DATE, 2020)

Proposing a Fast and Scalable Systolic Array for Matrix Multiplication. - Bahar Asgari; Ramyad Hadidi; Hyesoon Kim (FCCM, 2020)

ALRESCHA: A Lightweight Reconfigurable Sparse-Computation Accelerator. - Bahar Asgari; Ramyad Hadidi; Tushar Krishna; Hyesoon Kim; Sudhakar Yalamanchili (HPCA, 2020)

MEISSA: Multiplying Matrices Efficiently in a Scalable Systolic Architecture. - Bahar Asgari; Ramyad Hadidi; Hyesoon Kim (ICCD, 2020)

Edge-Tailored Perception: Fast Inferencing in-the-Edge with Efficient Model Distribution. - Ramyad Hadidi; Bahar Asgari; Jiashen Cao; Younmin Bae; Hyojong Kim; Michael S. Ryoo; Hyesoon Kim (CoRR, 2020)

Copernicus: Characterizing the Performance Implications of Compression Formats Used in Sparse Workloads. - Bahar Asgari; Ramyad Hadidi; Joshua Dierberger; Charlotte Steinichen; Hyesoon Kim (CoRR, 2020)

Quantifying the design-space tradeoffs in autonomous drones. - Ramyad Hadidi; Bahar Asgari; Sam Jijina; Adriana Amyette; Nima Shoghi; Hyesoon Kim (ASPLOS, 2021)

FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction. - Bahar Asgari; Ramyad Hadidi; Jiashen Cao; Da Eun Shim; Sung Kyu Lim; Hyesoon Kim (HPCA, 2021)

Copernicus: Characterizing the Performance Implications of Compression Formats Used in Sparse Workloads. - Bahar Asgari; Ramyad Hadidi; Joshua Dierberger; Charlotte Steinichen; Amaan Marfatia; Hyesoon Kim (IISWC, 2021)

Efficiently Solving Partial Differential Equations in a Partially Reconfigurable Specialized Hardware. - Bahar Asgari; Ramyad Hadidi; Tushar Krishna; Hyesoon Kim; Sudhakar Yalamanchili (IEEE Trans. Computers, 2021)

MAHASIM: Machine-Learning Hardware Acceleration Using a Software-Defined Intelligent Memory System. - Bahar Asgari; Saibal Mukhopadhyay; Sudhakar Yalamanchili (J. Signal Process. Syst., 2021)

Efficiently Accelerating Sparse Problems by Enabling Stream Accesses to Memory using Hardware/Software Techniques. - Bahar Asgari (2021)

Maia: Matrix Inversion Acceleration Near Memory. - Bahar Asgari; Dheeraj Ramchandani; Amaan Marfatia; Hyesoon Kim (FPL, 2022)

Creating Robust Deep Neural Networks with Coded Distributed Computing for IoT. - Ramyad Hadidi; Jiashen Cao; Bahar Asgari; Hyesoon Kim (EDGE, 2023)

Context-Aware Task Handling in Resource-Constrained Robots with Virtualization. - Ramyad Hadidi; Nima Shoghi Ghaleshahi; Bahar Asgari; Hyesoon Kim (EDGE, 2023)

Spica: Exploring FPGA Optimizations to Enable an Efficient SpMV Implementation for Computations at Edge. - Dheeraj Ramchandani; Bahar Asgari; Hyesoon Kim (EDGE, 2023)

Memory-Based Computing for Energy-Efficient AI: Grand Challenges. - Foroozan Karimzadeh; Mohsen Imani; Bahar Asgari; Ningyuan Cao; Yingyan Lin; Yan Fang (VLSI-SoC, 2023)

GUST: Graph Edge-Coloring Utilization for Accelerating Sparse Matrix Vector Multiplication. - Armin Gerami; Bahar Asgari (ASPLOS (4), 2024)

Acamar: A Dynamically Reconfigurable Scientific Computing Accelerator for Robust Convergence and Minimal Resource Underutilization. - Ubaid Bakhtiar; Helya Hosseini; Bahar Asgari (MICRO, 2024)

Misam: Using ML in Dataflow Selection of Sparse-Sparse Matrix Multiplication. - Sanjali Yadav; Bahar Asgari (CoRR, 2024)

Endor: Hardware-Friendly Sparse Format for Offloaded LLM Inference. - Donghyeon Joo; Ramyad Hadidi; Soheil Feizi; Bahar Asgari (CoRR, 2024)

La Superba: Leveraging a Self-Comparison Method to Understand the Performance Benefits of Sparse Acceleration Optimizations. - Nebil Ozer; Gregory Kollmer; Ramyad Hadidi; Bahar Asgari (ISPASS, 2025)

Segin: Synergistically Enabling Fine-Grained Multi-Tenant and Resource Optimized SpMV. - Helya Hosseini; Ubaid Bakhtiar; Donghyeon Joo; Bahar Asgari (IEEE Comput. Archit. Lett., 2025)

Electra: Eliminating the Ineffectual Computations on Bitmap Compressed Matrices. - Chaithanya Krishna Vadlamudi; Bahar Asgari (IEEE Comput. Archit. Lett., 2025)

DynaFlow: An ML Framework for Dynamic Dataflow Selection in SpGEMM Accelerators. - Sanjali Yadav; Bahar Asgari (IEEE Comput. Archit. Lett., 2025)

Mustafar: Promoting Unstructured Sparsity for KV Cache Pruning in LLM Inference. - Donghyeon Joo; Helya Hosseini; Ramyad Hadidi; Bahar Asgari (CoRR, 2025)