Design and Implementation of a Low-Power, Embedded CNN Accelerator on a Low-end FPGA. - Bahareh Khabbazan; Sattar Mirzakuchaki (DSD, 2019)

An Automated Tool for Implementing Deep Neural Networks on FPGA. - Masoud Shahshahani; Mohammad Sabri Abrebekoh; Bahareh Khabbazan; Dinesh Bhatia (VLSID, 2021)

Area and Power-Efficient Variable-Sized DCT Architecture for HEVC Using Muxed-MCM Problem. - Ahmad Shabani; Mohammad Sabri Abrebekoh; Bahareh Khabbazan; Somayeh Timarchi (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

QeiHaN: An Energy-Efficient DNN Accelerator that Leverages Log Quantization in NDP Architectures. - Bahareh Khabbazan; Marc Riera; Antonio González 001 (PACT, 2023)

DNA-TEQ: An Adaptive Exponential Quantization of Tensors for DNN Inference. - Bahareh Khabbazan; Marc Riera; Antonio González 001 (HiPC, 2023)

An Energy-Efficient Near-Data Processing Accelerator for DNNs that Optimizes Data Accesses. - Bahareh Khabbazan; Marc Riera; Antonio González 001 (CoRR, 2023)

An energy-efficient near-data processing accelerator for DNNs to optimize memory accesses. - Bahareh Khabbazan; Mohammad Sabri; Marc Riera; Antonio González 001 (J. Syst. Archit., 2025)

Towards Efficient LUT-based PIM: A Scalable and Low-Power Approach for Modern Workloads. - Bahareh Khabbazan; Marc Riera; Antonio González 001 (CoRR, 2025)