Automatic synthesis of a multi-bus architecture for DSP. - Baher Haroun; Mohamed I. Elmasry (ICCAD, 1988)

Architectural synthesis for DSP silicon compilers. - Baher Haroun; Mohamed I. Elmasry (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

SPAID: an architectural synthesis tool for DSP custom applications. - Baher Haroun; Mohamed I. Elmasry (IEEE J. Solid State Circuits, 1989)

Power estimation tool for sub-micron CMOS VLSI circuits. - F. Rouatbi; Baher Haroun; Asim J. Al-Khalili (ICCAD, 1992)

Synthesis of Multiple Bus/Functional Unit Architectures Implementing Neural Networks. - Baher Haroun; Elie Torbey (ICCD, 1992)

Optimal Datapath Synthesis of Partitioned Signal Processing Algorithm for Multiple FPGAs. - Baher Haroun; Behzard Sajjadi (ICCD, 1994)

A Novel Reduced Swing CMOS Bus Interface Circuit for High Speed Low Power VLSI Systems. - Reza Golshan; Baher Haroun (ISCAS, 1994)

A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic. - Baher Haroun; Chao Hua Wu (ISCAS, 1994)

A Floorplanner driven by Structural & Timing Constraints. - Abdelhakim Safir; Baher Haroun; Krishnaiyan Thulasiraman (ISCAS, 1994)

Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses. - Baher Haroun; Behzad Sajjadi (FPGA, 1995)

Floorplanning with Datapath Optimization. - Abdelhakim Safir; Baher Haroun; Krishnaiyan Thulasiraman (ISCAS, 1995)

A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities. - Prasun Raha; Scott Randall; Richard Jennings; Bob Helmick; Ajith Amerasekera; Baher Haroun (ISQED, 2002)

An embedded 0.8 V/480 μW 6b/22 MHz flash ADC in 0.13-μm digital CMOS process using a nonlinear double interpolation technique. - Jerry (Heng-Chih) Lin; Baher Haroun (IEEE J. Solid State Circuits, 2002)

A Sigma-Delta ADC with Decimation and Gain Control Function for a Bluetooth Receiver in 130 nm Digital CMOS. - Jinseok Koh; Gabriel Gomez; Khurram Muhammad; Robert Bogdan Staszewski; Baher Haroun (EURASIP J. Wirel. Commun. Netw., 2006)

A 110dB SNR and 0.5mW current-steering audio DAC implemented in 45nm CMOS. - Rahmi Hezar; Lars Risbo; Halil Kiper; Mounir Fares; Baher Haroun; Gangadhar Burra; Gabriel Gomez (ISSCC, 2010)

A 0.16mm2 completely on-chip switched-capacitor DC-DC converter using digital capacitance modulation for LDO replacement in 45nm CMOS. - Yogesh K. Ramadass; Ayman A. Fayed; Baher Haroun; Anantha P. Chandrakasan (ISSCC, 2010)

Session 16 overview: Switching power control techniques: Analog subcommittee. - Baher Haroun; Gyu-Hyeong Cho (ISSCC, 2012)

A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS. - Venkatesh Srinivasan; Victoria Wang; Patrick Satarzadeh; Baher Haroun; Marco Corsi (ISSCC, 2012)

Low power ADC's for wireless communications. - Vijay Rentala; Venkatesh Srinivasan; Victoria Wang; Srinath Ramaswamy; Baher Haroun; Marco Corsi (MWSCAS, 2012)

Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops. - Krishnaswamy Nagaraj; Anant S. Kamath; Karthik Subburaj; Biman Chattopadhyay; Gopalkrishna Nayak; Satyasai Evani; Neeraj P. Nayak; Indu Prathapan; Frank Zhang; Baher Haroun (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 29.5 dBm class-E outphasing RF power amplifier with performance enhancement circuits in 45nm CMOS. - Aritra Banerjee; Rahmi Hezar; Lei Ding 001; Nathan Schemm; Baher Haroun (ESSCIRC, 2014)

A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS. - Brian P. Ginsburg; Srinath Ramaswamy; Vijay Rentala; Eunyoung Seok; Swaminathan Sankaran; Baher Haroun (IEEE J. Solid State Circuits, 2014)

A 25 dBm Outphasing Power Amplifier With Cross-Bridge Combiners. - Lei Ding 001; Joonhoi Hur; Aritra Banerjee; Rahmi Hezar; Baher Haroun (IEEE J. Solid State Circuits, 2015)

A PWM Based Fully Integrated Digital Transmitter/PA for WLAN and LTE Applications. - Rahmi Hezar; Lei Ding 001; Aritra Banerjee; Joonhoi Hur; Baher Haroun (IEEE J. Solid State Circuits, 2015)

A 29.5 dBm Class-E Outphasing RF Power Amplifier With Efficiency and Output Power Enhancement Circuits in 45nm CMOS. - Aritra Banerjee; Rahmi Hezar; Lei Ding 001; Baher Haroun (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Autonomous Vehicles SEnsor Needs. - Baher Haroun (ESSDERC, 2018)

3.1 An Integrated BAW Oscillator with <±30ppm Frequency Stability Over Temperature, Package Stress, and Aging Suitable for High-Volume Production. - Danielle Griffith; Ernest Ting-Ta Yen; Kaichien Tsai; Habeeb Ur Rahman Mohammed; Baher Haroun; Ali Kiaei; Ahmad Bahai (ISSCC, 2020)

An Ultra-Low Close-In Phase Noise Series-Resonance BAW Oscillator in a 130-nm BiCMOS process. - Sachin Kalia; Bichoy Bahr; Tolga Dinc; Baher Haroun; Swaminathan Sankaran (A-SSCC, 2021)

A 770 kS/s Duty-Cycled Integrated-Fluxgate Magnetometer for Contactless Current Sensing. - Preet Garcha; Viola Schaffer; Baher Haroun; Srinath Ramaswamy; Jim Wieser; Jeffrey H. Lang; Anantha P. Chandrakasan (ISSCC, 2021)

High-Efficiency Class-E Power Amplifiers for mmWave Radar Sensors: Design and Implementation. - Tolga Dinc; Sachin Kalia; Siraj Akhtar; Baher Haroun; Benjamin Cook; Swaminathan Sankaran (IEEE J. Solid State Circuits, 2022)

A Duty-Cycled Integrated-Fluxgate Magnetometer for Current Sensing. - Preet Garcha; Viola Schaffer; Baher Haroun; Srinath Ramaswamy; Jim Wieser; Jeffrey H. Lang; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2022)

A Sub-100 Fs RMSjitter 20 GHz Fractional-N Analog PLL With a BAW Resonator Based On-Chip 2.5 GHz Reference. - Sachin Kalia; Salvatore Finocchiaro; Tolga Dinc; Bichoy Bahr; Ashwin Raghunathan; Gerd Schuppener; Siraj Akhtar; Tobias Fritz; Baher Haroun; Benjamin Cook; Swaminathan Sankaran (IEEE J. Solid State Circuits, 2022)

High-Linearity High-Bandwidth (>20GHz) T&H Front Ends Using Active Bootstrapping and Heterogeneous SiGe/CMOS Circuit Co-Design. - Athanasios Ramkaj; Michael Perrott; Baher Haroun; Boris Murmann (ISCAS, 2023)

A 0.5-to-400MHz Programmable BAW Oscillator with Fractional Output Divider Achieving 4ppm Frequency Stability over Temperature and <95fs Jitter. - Subhashish Mukherjee; Yogesh Darwhekar; Jayawardan Janardhanan; Peeyoosh Mirajkar; Raghavendra Reddy; Harish Ramesh; Bichoy Bahr; Jagdish Chand; Uday Meda; Baher Haroun; Shankar Karantha; Ernest Ting-Ta Yen; et al. (ISSCC, 2023)

A Sub-THz CMOS Transceiver IC and System for Medium-Reach Guided Wave and Short-Reach Wireless Communication Links. - Swaminathan Sankaran; Gerd Schuppener; Juan Herbsommer; Bradley Kramer; Hassan Ali; Robert Payne; Carole Rush; Baher Haroun; Nirmal Warke (MWSCAS, 2024)