Ultrathin Compound Semiconductor in Bulk Planar Junctionless Transistor for High-Performance Nanoscale Transistors. - Bahniman Ghosh; Uzma Khan; Ball Mukund Mani Tripathi; M. W. Akram (J. Low Power Electron., 2013)

A Novel Approach of Full Adder and Arithmetic Logic Unit Design in Quantum Dot Cellular Automata. - Bahniman Ghosh; Chandramauli Singh; Akshay Kumar Salimath (J. Low Power Electron., 2013)

Junctionless Tunnel Field Effect Transistor with Enhanced Performance Using III-V Semiconductor. - Yogesh Goswami; Ball Mukund Mani Tripathi; Pranav Kumar Asthana; Bahniman Ghosh (J. Low Power Electron., 2013)

Effect of Self Heating on Selective Buried Oxide and Silicon on Insulator Based Junctionless Transistors. - Uzma Khan; Bahniman Ghosh; M. W. Akram (J. Low Power Electron., 2013)

Performance Analysis of Spin Transfer Torque Random Access Memory with cross shaped free layer using Heusler Alloys by using micromagnetic studies. - Tangudu Bharat Kumar; Bhaskar Awadhiya; E. MeherAbhinav; Bahniman Ghosh; Bhupesh Bishnoi (CoRR, 2014)

Transistor size optimization in digital circuits using ant colony optimization for continuous domain. - Himanshu Gupta; Bahniman Ghosh (Int. J. Circuit Theory Appl., 2014)

Design of a Multi-Layered QCA Configurable Logic Block for FPGAs. - Bahniman Ghosh; Jangam Siva Chandra; Akshay Kumar Salimath (J. Circuits Syst. Comput., 2014)

Junctionless Silicon-Nanowire Gate-All-Around Tunnel Field Effect Transistor. - M. W. Akram; Bahniman Ghosh (J. Low Power Electron., 2014)

Effect of Traps on the Performance of Nanowire Si Junctionless Tunnel FET. - Shibir Basak; Bahniman Ghosh (J. Low Power Electron., 2014)

Simulation of 2 Bit by 2 Bit Binary Multiplier Using Magnetic Tunnel Junction Device. - Yuvaneet Bhaker; Princepreet Singh; Bahniman Ghosh (J. Low Power Electron., 2014)

Clocking Scheme Implementation for Multi-Layered Quantum Dot Cellular Automata Design. - Jangam Siva Chandra; Kandula Suresh; Bahniman Ghosh (J. Low Power Electron., 2014)

2-Bit Full Adder Implementation Using Single Spin Logic Paradigm. - Bahniman Ghosh; A. Ajay (J. Low Power Electron., 2014)

Performance Improvement in Nanoscale Ge-GaAs Heterojunction Junctionless Tunnel FET Using a Dual Material Gate. - Bahniman Ghosh; Shibir Basak; Pranav Kumar Asthana (J. Low Power Electron., 2014)

Device Physics of Germanium-Junctionless Tunnel Field Effect Transistor and an Approach to Optimize I on/I off by Drain Engineering and Work Function Engineering. - Bahniman Ghosh; Punyasloka Bal; Partha Mondal; M. W. Akram (J. Low Power Electron., 2014)

Spin Transport in Single Layer Germanene: The Role of Electron Electron Scattering. - Bahniman Ghosh; Aayush Gupta (J. Low Power Electron., 2014)

Effect of Nanoribbon Width and Strain on the Electronic Properties of the WS2 Nanoribbon. - Bahniman Ghosh; Aayush Gupta (J. Low Power Electron., 2014)

Quantum-Dot Cellular Automata-Implementing Reversible Benchmarks. - Bahniman Ghosh; Abhinay Kumar (J. Low Power Electron., 2014)

Impact of High- Spacer on Junctionless Transistor in Sub-Threshold Regime. - Bahniman Ghosh; Partha Mondal; M. W. Akram; Punyasloka Bal (J. Low Power Electron., 2014)

In0 25Ga0 75As Channel Double Gate Junctionless Transistor. - Bahniman Ghosh; Neelam Surana; M. W. Akram; Ball Mukund Mani Tripathi (J. Low Power Electron., 2014)

Domain Wall Dynamics Due to Voltage Controlled Magnetic Anisotropy. - Bahniman Ghosh; Gaurav S. Solanki; Abhishek Banerjee (J. Low Power Electron., 2014)

Read and Write Analysis for Balanced Pattern Memristor Crossbar Array. - Arun Kant Sharma; Shiva Asapu; Akshay Kumar Salimath; Bahniman Ghosh (J. Low Power Electron., 2014)

Ab-Initio Modeling of Effect of Boron and Phosphorus Doping in CoFe/MgO Magnetic Tunnel Junctions. - Ankit Kumar Verma; Bahniman Ghosh; Bhaskar Awadhiya; Tangudu Bharat Kumar (J. Low Power Electron., 2014)

Innovative design methodologies in quantum-dot cellular automata. - Puneet Agrawal; Bahniman Ghosh (Int. J. Circuit Theory Appl., 2015)