A 1.97 TFLOPS/W Configurable SRAM-Based Floating-Point Computation-in-Memory Macro for Energy-Efficient AI Chips. - Yangzhan Mai; Mingyu Wang 003; Chuanghao Zhang; Baiqing Zhong; Zhiyi Yu (ISCAS, 2023)

A Digital SRAM Computing-in-Memory Design Utilizing Activation Unstructured Sparsity for High-Efficient DNN Inference. - Baiqing Zhong; Mingyu Wang 003; Chuanghao Zhang; Yangzhan Mai; Xiaojie Li; Zhiyi Yu (ISVLSI, 2023)

CCacheSim: A Circuit-Architecture Cross-Level Simulation Framework for SRAM-Based in-Cache Computing System Evaluation. - Baiqing Zhong; Mingyu Wang; Yicong Zhang; Xiaojie Li; Zhiyi Yu (ICCD, 2024)

BafSP: Co-Design of Compute SRAM and Bit-Aware Data Flip Mitigation with In-Memory Sparsity Detection for SpMM. - Xiaojie Li; Mingyu Wang 003; Yangzhan Mai; Yicong Zhang; Baiqing Zhong; Zhiyi Yu (ISVLSI, 2024)