Terrestrial SER characterization for nanoscale technologies: A comparative study. - Nihaar N. Mahatme; Bharat L. Bhuva; Nelson J. Gaspard; T. Assis; Y. Xu; P. Marcoux; M. Vilchis; Balaji Narasimham; A. Shih; Shi-Jie Wen; Rick Wong; N. Tam; et al. (IRPS, 2015)

Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs. - Balaji Narasimham; Jung K. Wang; Narayana Vedula; Saket Gupta; Brandon Bartz; Carl Monzel; Indranil Chatterjee; Bharat L. Bhuva; Ronald D. Schrimpf; Robert A. Reed (IRPS, 2015)

Designing soft-error-aware circuits with power and speed optimization. - H. Jiang; H. Zhang; Balaji Narasimham; Lloyd W. Massengill; Bharat L. Bhuva (IRPS, 2018)

Scaling trends and bias dependence of the soft error rate of 16 nm and 7 nm FinFET SRAMs. - Balaji Narasimham; Saket Gupta; Daniel S. Reed; J. K. Wang; Nick Hendrickson; Hasan Taufique (IRPS, 2018)

Evaluation of the system-level SER performance of gigabit ethernet transceiver devices. - Balaji Narasimham; Tim Wu; Jung K. Wang; Bruce Conway (IRPS, 2018)

Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology. - H. Zhang; H. Jiang; M. R. Eaker; Kurt J. Lezon; Balaji Narasimham; Nihaar N. Mahatme; Lloyd W. Massengill; Bharat L. Bhuva (IRPS, 2018)

Alpha Particle Soft-Error Rates for D-FF Designs in 16-Nm and 7-Nm Bulk FinFET Technologies. - Jingchen Cao; Lyuan Xu; Bharat L. Bhuva; Shi-Jie Wen; Richard Wong; Balaji Narasimham; Lloyd W. Massengill (IRPS, 2019)

Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes. - Balaji Narasimham; K. Chandrasekharan; J. K. Wang; Bharat L. Bhuva (IRPS, 2019)

Temperature Dependence of Single-Event Transient Pulse Widths for 7-nm Bulk FinFET Technology. - Jingchen Cao; Lyuan Xu; Shi-Jie Wen; Rita Fung; Balaji Narasimham; Lloyd W. Massengill; Bharat L. Bhuva (IRPS, 2020)

Effects of Temperature and Supply Voltage on Soft Errors for 7-nm Bulk FinFET Technology. - Alexandra Feeley; Yoni Xiong; Bharat L. Bhuva; Balaji Narasimham; Shi-Ji Wen; Rita Fung (IRPS, 2021)

Scaling Trends in the Soft Error Rate of SRAMs from Planar to 5-nm FinFET. - Balaji Narasimham; Vikas Chaudhary; Mike Smith; Liming Tsau; Dennis R. Ball; Bharat L. Bhuva (IRPS, 2021)

Soft Error Characterization of D-FFs at the 5-nm Bulk FinFET Technology for the Terrestrial Environment. - Yoni Xiong; Alexandra Feeley; Nicholas J. Pieper; Dennis R. Ball; Balaji Narasimham; John Brockman; N. A. Dodds; S. A. Wender; Shi-Jie Wen; Rita Fung; Bharat L. Bhuva (IRPS, 2022)

Scaling Trends and the Effect of Process Variations on the Soft Error Rate of advanced FinFET SRAMs. - Balaji Narasimham; H. Luk; C. Paone; A-R. Montoya; T. Riehle; Mike Smith; Liming Tsau (IRPS, 2023)

Scaling Trends and Bias Dependence of SRAM SER from 16-nm to 3-nm FinFET. - Balaji Narasimham; A-R. Montoya; C. Paone; T. Riehle; Mike Smith; Liming Tsau; Dennis R. Ball; Bharat L. Bhuva (IRPS, 2024)