Leakage Optimized DECAP Design for FPGAs. - Balaji Vaidyanathan; Suresh Srinivasan; Yuan Xie 001; Narayanan Vijaykrishnan; Rong Luo (APCCAS, 2006)

Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression. - Balaji Vaidyanathan; Yuan Xie 001 (SoCC, 2006)

A Process Scheduler-Based Approach to NoC Power Management. - Feihui Li; Guilin Chen; Mahmut T. Kandemir; Ozcan Ozturk 001; Mustafa Karaköy; Rajaraman Ramanarayanan; Balaji Vaidyanathan (VLSI Design, 2007)

Architecting Microprocessor Components in 3D Design Space. - Balaji Vaidyanathan; Wei-Lun Hung; Feng Wang 004; Yuan Xie 001; Narayanan Vijaykrishnan; Mary Jane Irwin (VLSI Design, 2007)

Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model. - Feng Wang 004; Yuan Xie 001; R. Rajaraman; Balaji Vaidyanathan (VLSI Design, 2007)

Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors. - Liping Xue; Mahmut T. Kandemir; Guilin Chen; Feihui Li; Ozcan Ozturk 001; Rajaraman Ramanarayanan; Balaji Vaidyanathan (VLSI Design, 2007)

Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning. - Balaji Vaidyanathan; Anthony S. Oates; Yuan Xie 001 (ICCAD, 2009)

NBTI-aware statistical circuit delay assessment. - Balaji Vaidyanathan; Anthony S. Oates; Yuan Xie 001; Yu Wang 002 (ISQED, 2009)