Multi-core processors - An overview - Balaji Venu (CoRR, 2011)

Formal verification methodology considerations for network on chips. - Balaji Venu; Ashwani Singh (ICACCI, 2012)

Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPU. - Xabier Iturbe; Balaji Venu; Emre Ozer 001 (DFT, 2016)

A Triple Core Lock-Step (TCLS) ARM® Cortex®-R5 Processor for Safety-Critical and Ultra-Reliable Applications. - Xabier Iturbe; Balaji Venu; Emre Ozer 001; Shidhartha Das (DSN Workshops, 2016)

A "high resilience" mode to minimize soft error vulnerabilities in ARM cortex-R CPU pipelines: work-in-progress. - Xabier Iturbe; Balaji Venu; John Penton; Emre Ozer 001 (CASES, 2017)

Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems. - Emre Ozer 001; Balaji Venu; Xabier Iturbe; Shidhartha Das; Spyros Lyberis; John Biggs; Peter Harrod; John Penton (MICRO, 2018)

Addressing Functional Safety Challenges in Autonomous Vehicles with the Arm TCL S Architecture. - Xabier Iturbe; Balaji Venu; Juergen Jagst; Emre Ozer 001; Peter Harrod; Chris Turner; John Penton (IEEE Des. Test, 2018)

The Arm Triple Core Lock-Step (TCLS) Processor. - Xabier Iturbe; Balaji Venu; Emre Ozer 001; Jean-Luc Poupat; Gregoire Gimenez; Hans-Ulrich Zurek (ACM Trans. Comput. Syst., 2018)

Industrial Challenge 2022: A High-Performance Real-Time Case Study on Arm. - Matteo Andreozzi; Giacomo Gabrielli; Balaji Venu; Giacomo Travaglini (ECRTS, 2022)

Characterization of a Coherent Hardware Accelerator Framework for SoCs. - Guillem López-Paradís; Balaji Venu; Adrià Armejach; Miquel Moretó (SAMOS, 2023)