Application debug in FPGAs in the presence of multiple asynchronous clocks. - Georgios Tzimpragos; Da Cheng; Stephanie Tapp; Balakrishna Jayadev; Amitava Majumdar 002 (FPT, 2016)

Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs. - Amitava Majumdar 002; Balakrishna Jayadev; Da Cheng; Albert Lin (ATS, 2017)

Handling Clock-Domain Crossings in Dual Clock-Edge Logic for DFx Features. - Amitava Majumdar 002; Balakrishna Jayadev (ATS, 2018)