FPGA design and implementation of truncated multipliers using bypassing technique. - S. Balamurugan 001; Balakumaran Srirangaswamy; R. Marimuthu 001; Partha Sharathi Mallick (ICACCI, 2012)

Design of low power fixed-width multiplier with row bypassing. - S. Balamurugan 001; Sneha Ghosh; Atul; Balakumaran Srirangaswamy; R. Marimuthu 001; Partha Sharathi Mallick (IEICE Electron. Express, 2012)