Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect. - Roman Kuznar; Franc Brglez; Baldomir Zajc (DAC, 1994)

A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions. - Roman Kuznar; Baldomir Zajc; Franc Brglez (EURO-DAC, 1994)

A Functionality Fault Model: Feasibility and Applications. - Andrej Zemva; Franc Brglez; Krzysztof Kozminski; Baldomir Zajc (EDAC-ETC-EUROASIC, 1994)

An Experimental Programmable Environment for Prototyping Digital Circuits. - Andrej Trost; Roman Kuznar; Andrej Zemva; Baldomir Zajc (FPL, 1996)

Programmabel Prototyping System for Image Processing. - Andrej Trost; Andrej Zemva; Baldomir Zajc (FPL, 1998)

Educational Programmable Hardware Prototyping and Verification System. - Andrej Trost; Andrej Zemva; Baldomir Zajc (FPL, 2000)

Optimization of FPGA configurations using parallel genetic algorithm. - Hubert Fröhlich; Andrej Koir; Baldomir Zajc (Inf. Sci., 2001)

Test generation for technology-specific multi-faults based on detectable perturbations. - Andrej Zemva; Baldomir Zajc (Microelectron. Reliab., 2005)

Logic emulators in digital systems education. - Andrej Trost; Baldomir Zajc (EUROCON, 2011)