Efficient nanoscale VLSI standard cell library characterization using a novel delay model. - Sandeep Miryala; Baljit Kaur; Bulusu Anand; Sanjeev Manhas (ISQED, 2011)

An accurate current source model for CMOS based combinational logic cell. - Baljit Kaur; Sandeep Vundavalli; S. K. Manhas; Sudeb Dasgupta; Bulusu Anand (ISQED, 2012)

Novel VLSI architecture for two-dimensional radon transform computations. - Baljit Kaur; Manoj Kumar Majumder (RAIT, 2012)

An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies. - Baljit Kaur; Sandeep Miryala; S. K. Manhas; Bulusu Anand (ISQED, 2013)

Efficient ECSM Characterization Considering Voltage, Temperature, and Mechanical Stress Variability. - Baljit Kaur; Naushad Alam; S. K. Manhas; Bulusu Anand (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Timing model for two stage buffer and its application in ECSM characterization. - Yogesh Chaurasiya; Surabhi Bhargava; Arvind Kumar Sharma; Baljit Kaur; Bulusu Anand (VDAT, 2015)

A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization. - Baljit Kaur; Arvind Kumar Sharma; Naushad Alam; S. K. Manhas; Bulusu Anand (Microelectron. J., 2016)

A scene perception system for visually impaired based on object detection and classification using multi-modal DCNN. - Baljit Kaur; Jhilik Bhattacharya (CoRR, 2018)

A convolutional feature map-based deep network targeted towards traffic detection and classification. - Baljit Kaur; Jhilik Bhattacharya (Expert Syst. Appl., 2019)

Scene perception system for visually impaired based on object detection and classification using multimodal deep convolutional neural network. - Baljit Kaur; Jhilik Bhattacharya (J. Electronic Imaging, 2019)

Performance analysis of Pocket Doped Junction-Less TFET. - Sneha Bharti; Suruchi Sharma; Abhishek Verma; Manisha Bharti; Baljit Kaur (ISDCS, 2020)

Design of Tunnel Junction Engineered Dopingless TFET for Low power Applications. - Abhishek Verma; Suruchi Sharma; Sneha Bharti; Manisha Bharti; Baljit Kaur (ISDCS, 2020)

Performance investigation of asymmetric double-gate doping less tunnel FET with Si/Ge heterojunction. - Suruchi Sharma; Baljit Kaur (IET Circuits Devices Syst., 2020)

A Hybrid Approach for Scene Matching used for Autonomous vehicles. - Baljit Kaur; Jhilik Bhattacharya (ICC Workshops, 2021)

DC and linearity performance of a novel Si0.6Ge0.4/Ge Dopingless Tunnel FET for ultra-low voltage applications. - Suruchi Sharma; Rikmantra Basu; Baljit Kaur (ISDCS, 2021)

Performance Investigation of a Si/Ge Heterojunction Asymmetric Double Gate DLTFET Considering Temperature and ITC Variations. - Suruchi Sharma; Rikmantra Basu; Baljit Kaur (ISQED, 2021)

Interface trap charges associated reliability analysis of Si/Ge heterojunction dopingless TFET. - Suruchi Sharma; Rikmantra Basu; Baljit Kaur (IET Circuits Devices Syst., 2021)

Architectural analysis of 1-D to 2-D array conversion of priority encoder. - Alok Kumar Mishra 001; Shail Anand; Nishant Singh; Vaithiyanathan Dhandapani; Baljit Kaur (Int. J. Syst. Assur. Eng. Manag., 2023)

Design insights into a junctionless nanosheet FET (JL-NSFET) for switching and Analog/RF applications: Device to circuit level assessment. - Vadthya Bheemudu; Vaithiyanathan Dhandapani; Baljit Kaur (Microelectron. J., 2024)