A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI. - Dongsheng Yang 002; Wei Deng 001; Aravind Tharayil Narayanan; Rui Wu 001; Bangan Liu; Kenichi Okada 001; Akira Matsuzawa (IEICE Electron. Express, 2015)

An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. - Dongsheng Yang 002; Wei Deng 001; Bangan Liu; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2016)

13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay. - Rui Wu 001; Seitaro Kawai; Yuuki Seo; Nurul Fajri; Kento Kimura; Shinji Sato; Satoshi Kondo; Tomohiro Ueno; Teerachot Siriburanon; Shoutarou Maki; Bangan Liu; Yun Wang 008; et al. (ISSCC, 2016)

Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network. - Rui Wu 001; Ryo Minami; Yuuki Tsukui; Seitaro Kawai; Yuuki Seo; Shinji Sato; Kento Kimura; Satoshi Kondo; Tomohiro Ueno; Nurul Fajri; Shoutarou Maki; Noriaki Nagashima; et al. (ASICON, 2017)

An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. - Dongsheng Yang 002; Wei Deng 001; Bangan Liu; Aravind Tharayil Narayanan; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2017)

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance. - Jian Pang; Shotaro Maki; Seitarou Kawai; Noriaki Nagashima; Yuuki Seo; Masato Dome; Hisashi Kato; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Yuki Terashima; Hanli Liu; et al. (ISSCC, 2017)

64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay. - Rui Wu 001; Ryo Minami; Yuuki Tsukui; Seitaro Kawai; Yuuki Seo; Shinji Sato; Kento Kimura; Satoshi Kondo; Tomohiro Ueno; Nurul Fajri; Shoutarou Maki; Noriaki Nagashima; et al. (IEEE J. Solid State Circuits, 2017)

A 28.16-Gb/s Area-Efficient 60GHz CMOS Bi-Directional Transceiver for IEEE 802.11ay. - Jian Pang; Korkut Kaan Tokgoz; Shotaro Maki; Zheng Li 021; Xueting Luo; Ibrahim Abdo; Seitarou Kawai; Hanli Liu; Bangan Liu; Makihiko Katsuragi; Kento Kimura; Atsushi Shirane; et al. (A-SSCC, 2018)

A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. - Bangan Liu; Huy Cu Ngo; Kengo Nakata; Wei Deng 001; Yuncheng Zhang; Junjun Qiu; Toru Yoshioka; Jun Emmei; Haosheng Zhang; Jian Pang; Aravind Tharayil Narayanan; Dongsheng Yang 002; et al. (CICC, 2018)

A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS. - Bangan Liu; Yun Wang 008; Jian Pang; Haosheng Zhang; Dongsheng Yang 002; Aravind Tharayil Narayanan; Dae Young Lee; Sung Tae Choi; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2018)

An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration. - Bangan Liu; Yuncheng Zhang; Junjun Qiu; Wei Deng 001; Zule Xu; Haosheng Zhang; Jian Pang; Yun Wang 008; Rui Wu 001; Teruki Someya; Atsushi Shirane; Kenichi Okada 001 (CICC, 2019)

A 78 fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO. - Zheng Sun 001; Hanli Liu; Dingxin Xu; Hongye Huang; Bangan Liu; Zheng Li 021; Jian Pang; Teruki Someya; Atsushi Shirane (ESSCIRC, 2019)

A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR. - Jian Pang; Zheng Li 021; Ryo Kubozoe; Xueting Luo; Rui Wu 001; Yun Wang 008; Dongwon You; Ashbir Aviat Fadila; Rattanan Saengchan; Takeshi Nakamura; Joshua Alvin; Daiki Matsumoto; et al. (ISSCC, 2019)

0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur. - Haosheng Zhang; Aravind Tharayil Narayanan; Hans Herdian; Bangan Liu; Yun Wang 008; Atsushi Shirane; Kenichi Okada 001 (VLSI Circuits, 2019)

A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock. - Haosheng Zhang; Aravind Tharayil Narayanan; Hans Herdian; Bangan Liu; Rui Wu 001; Atsushi Shirane; Kenichi Okada 001 (IEICE Trans. Electron., 2019)

A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance. - Jian Pang; Shotaro Maki; Seitarou Kawai; Noriaki Nagashima; Yuuki Seo; Masato Dome; Hisashi Kato; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Yuki Terashima; Hanli Liu; et al. (IEEE J. Solid State Circuits, 2019)

A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio. - Jian Pang; Rui Wu 001; Yun Wang 008; Masato Dome; Hisashi Kato; Hongye Huang; Aravind Tharayil Narayanan; Hanli Liu; Bangan Liu; Takeshi Nakamura; Takuya Fujimura; Masaru Kawabuchi; et al. (IEEE J. Solid State Circuits, 2019)

A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS. - Yun Wang 008; Bangan Liu; Rui Wu 001; Hanli Liu; Aravind Tharayil Narayanan; Jian Pang; Ning Li 009; Toru Yoshioka; Yuki Terashima; Haosheng Zhang; Dexian Tang; Makihiko Katsuragi; et al. (IEEE J. Solid State Circuits, 2019)

A 28GHz CMOS Differential Bi-Directional Amplifier for 5G NR. - Zheng Li 021; Jian Pang; Ryo Kubozoe; Xueting Luo; Rui Wu 001; Yun Wang 008; Dongwon You; Ashbir Aviat Fadila; Joshua Alvin; Bangan Liu; Zheng Sun 001; Hongye Huang; et al. (ASP-DAC, 2020)

A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation. - Jian Pang; Zheng Li 021; Xueting Luo; Joshua Alvin; Rattanan Saengchan; Ashbir Aviat Fadila; Kiyoshi Yanagisawa; Yi Zhang 092; Zixin Chen; Zhongliang Huang; Xiaofan Gu; Rui Wu 001; et al. (VLSI Circuits, 2020)

A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL. - Yuncheng Zhang; Bangan Liu; Xiaofan Gu; Chun Wang; Kiyoshi Yanagisawa; Junjun Qiu; Yun Wang 008; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (VLSI Circuits, 2020)

A Compact TF-Based LC-VCO with Ultra-Low-Power Operation and Supply Pushing Reduction for IoT Applications. - Zheng Sun 001; Dingxin Xu; Hongye Huang; Zheng Li 021; Hanli Liu; Bangan Liu; Jian Pang; Teruki Someya; Atsushi Shirane; Kenichi Okada 001 (IEICE Trans. Electron., 2020)

A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR. - Jian Pang; Zheng Li 021; Ryo Kubozoe; Xueting Luo; Rui Wu 001; Yun Wang 008; Dongwon You; Ashbir Aviat Fadila; Rattanan Saengchan; Takeshi Nakamura; Joshua Alvin; Daiki Matsumoto; et al. (IEEE J. Solid State Circuits, 2020)

A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS. - Yun Wang 008; Rui Wu 001; Jian Pang; Dongwon You; Ashbir Aviat Fadila; Rattanan Saengchan; Xi Fu; Daiki Matsumoto; Takeshi Nakamura; Ryo Kubozoe; Masaru Kawabuchi; Bangan Liu; et al. (IEEE J. Solid State Circuits, 2020)

A DSM-based Polar Transmitter with 23.8% System Efficiency. - Yuncheng Zhang; Bangan Liu; Xiaofan Gu; Chun Wang; Atsushi Shirane; Kenichi Okada 001 (ASP-DAC, 2021)

A 0.25 mm2 BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration. - Zheng Sun 001; Dingxin Xu; Junjun Qiu; Zezheng Liu; Yuncheng Zhang; Hongye Huang; Hanli Liu; Bangan Liu; Zheng Li 021; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (ESSCIRC, 2021)

32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth. - Junjun Qiu; Zheng Sun 001; Bangan Liu; Wenqian Wang; Dingxin Xu; Hans Herdian; Hongye Huang; Yuncheng Zhang; Yun Wang 008; Atsushi Shirane; Kenichi Okada 001 (ISSCC, 2021)

A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems. - Jian Pang; Zheng Li 021; Xueting Luo; Joshua Alvin; Rattanan Saengchan; Ashbir Aviat Fadila; Kiyoshi Yanagisawa; Yi Zhang 092; Zixin Chen; Zhongliang Huang; Xiaofan Gu; Rui Wu 001; et al. (IEEE J. Solid State Circuits, 2021)

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth. - Junjun Qiu; Zheng Sun 001; Bangan Liu; Wenqian Wang; Dingxin Xu; Hans Herdian; Hongye Huang; Yuncheng Zhang; Yun Wang 008; Jian Pang; Hanli Liu; Masaya Miyahara; et al. (IEEE J. Solid State Circuits, 2021)

A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration. - Bangan Liu; Yuncheng Zhang; Junjun Qiu; Huy Cu Ngo; Wei Deng 001; Kengo Nakata; Toru Yoshioka; Jun Emmei; Jian Pang; Aravind Tharayil Narayanan; Haosheng Zhang; Teruki Someya; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A low-power digital baseband circuit for GMSK demodulation in sub-GHz application. - Junjun Qiu; Bangan Liu; Yuncheng Zhang; Atsushi Shirane; Kenichi Okada 001 (IEICE Electron. Express, 2022)

A 0.37mm2 Fully-Integrated Wide Dynamic Range Sub-GHz Receiver Front-End without Off-Chip Matching Components. - Yuncheng Zhang; Bangan Liu; Teruki Someya; Rui Wu 001; Junjun Qiu; Atsushi Shirane; Kenichi Okada 001 (IEICE Trans. Electron., 2022)

A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal. - Yun Wang 008; Dongwon You; Xi Fu; Takeshi Nakamura; Ashbir Aviat Fadila; Teruki Someya; Atsuhiro Kawaguchi; Junjun Qiu; Jian Pang; Kiyoshi Yanagisawa; Bangan Liu; Yuncheng Zhang; et al. (IEEE J. Solid State Circuits, 2022)

A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference. - Dingxin Xu; Yuncheng Zhang; Hongye Huang; Zheng Sun 001; Bangan Liu; Ashbir Aviat Fadila; Junjun Qiu; Zezheng Liu; Wenqian Wang; Yuang Xiong; Waleed Madany; Atsushi Shirane; et al. (CICC, 2023)

A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration. - Junjun Qiu; Wenqian Wang; Zheng Sun 001; Bangan Liu; Yuncheng Zhang; Dingxin Xu; Hongye Huang; Ashbir Aviat Fadila; Zezheng Liu; Waleed Madany; Yuang Xiong; Atsushi Shirane; et al. (ISSCC, 2023)

A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Transformer Combined FIR FIlter. - Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Junjun Qiu; Dingxin Xu; Yi Zhang 092; Xi Fu; Dongwon You; Hongye Huang; Waleed Madany; Ashbir Aviat Fadila; Zezheng Liu; et al. (VLSI Technology and Circuits, 2023)

10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter. - Dingxin Xu; Zezheng Liu; Yifeng Kuai; Hongye Huang; Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Wenqian Wang; Yuang Xiong; Junjun Qiu; Waleed Madany; Yi Zhang 092; et al. (ISSCC, 2024)

A synthesizable spread spectrum clock generator based on type-II/III fractional-N DPLL. - Waleed Madany; Hongye Huang; Bangan Liu; Ashbir Aviat Fadila; Zezheng Liu; Wenqian Wang; Junjun Qiu; Jill C. Mayeda; Atsushi Shirane; Kenichi Okada 001 (IEICE Electron. Express, 2024)

A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter. - Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Junjun Qiu; Dingxin Xu; Yi Zhang 092; Xi Fu; Dongwon You; Hongye Huang; Waleed Madany; Ashbir Aviat Fadila; Zezheng Liu; et al. (IEEE J. Solid State Circuits, 2024)

NLJM: A Simplified Jitter Model of Digital Standard Cells for Rapid Automatic Design of Frequency Synthesizers. - Hongye Huang; Ashbir Aviat Fadila; Dingxin Xu; Waleed Madany; Wenqian Wang; Zezheng Liu; Yuang Xiong; Tianshi Hu; Bangan Liu; Yuncheng Zhang; Atsushi Shirane; Kenichi Okada 001 (IEEE Access, 2025)

A 6.5-to-8-GHz Cascaded Dual-Fractional-N Digital PLL Achieving -52.79-dBc Fractional Spur With 50-MHz Reference. - Dingxin Xu; Yuncheng Zhang; Hongye Huang; Zheng Sun 001; Bangan Liu; Ashbir Aviat Fadila; Junjun Qiu; Zezheng Liu; Wenqian Wang; Yuang Xiong; Waleed Madany; Atsushi Shirane; et al. (IEEE J. Solid State Circuits, 2025)

A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a - 62.1-dBc Fractional Spur. - Dingxin Xu; Zezheng Liu; Yifeng Kuai; Hongye Huang; Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Wenqian Wang; Yuang Xiong; Junjun Qiu; Waleed Madany; Yi Zhang 092; et al. (IEEE J. Solid State Circuits, 2025)