Auxiliary testability design schemes for CMOS DACs with ultrahigh sampling rates. - Bao Li 003; Long Zhao; Yuhua Cheng (ASICON, 2017)

A 6-bit 700-MS/s single-channel SAR ADC with low kickback noise comparator in 40-nm CMOS. - Long Zhao; Bao Li 003; Yuhua Cheng (ASICON, 2017)

Duty Cycle Distortion in Half-rate Nyquist DACs with Limited Output Bandwidth. - Bao Li 003; Long Zhao; Jiangfeng Wu; Yuhua Cheng (ISCAS, 2018)

A 12GS/s 6-bit DAC with 4-2 Segmentation in 40nm CMOS. - Bao Li 003; Long Zhao; Jiangfeng Wu; Yuhua Cheng (ISCAS, 2018)

A 4 GS/s 6-bit 4-2 segmented current-steering DAC with compact current cells. - Bao Li 003; Long Zhao; Yuhua Cheng (IEICE Electron. Express, 2018)

A 700-MS/s 6-bit SAR ADC with partially active reference voltage buffer. - Long Zhao; Bao Li 003; Yuhua Cheng (IEICE Electron. Express, 2018)