Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control. - Charles J. Alpert; Andrew B. Kahng; Bao Liu 001; Ion I. Mandoiu; Alexander Zelikovsky (ICCAD, 2001)

Buffered Steiner trees for difficult instances. - Charles J. Alpert; Milos Hrkic; Jiang Hu; Andrew B. Kahng; John Lillis; Bao Liu 001; Stephen T. Quay; Sachin S. Sapatnekar; A. J. Sullivan; Paul Villarrubia (ISPD, 2001)

Interconnect implications of growth-based structural models for VLSI circuits. - Chung-Kuan Cheng; Andrew B. Kahng; Bao Liu 001 (SLIP, 2001)

Non-tree routing for reliability and yield improvement. - Andrew B. Kahng; Bao Liu 001; Ion I. Mandoiu (ICCAD, 2002)

Toward better wireload models in the presence of obstacles. - Chung-Kuan Cheng; Andrew B. Kahng; Bao Liu 001; Dirk Stroobandt (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization. - Andrew B. Kahng; Bao Liu 001 (ISVLSI, 2003)

On the skew-bounded minimum-buffer routing tree problem. - Christoph Albrecht; Andrew B. Kahng; Bao Liu 001; Ion I. Mandoiu; Alexander Zelikovsky (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Minimum buffered routing with bounded capacitive load for slew rate and reliability control. - Charles J. Alpert; Andrew B. Kahng; Bao Liu 001; Ion I. Mandoiu; Alexander Zelikovsky (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Nontree routing for reliability and yield improvement [IC layout]. - Andrew B. Kahng; Bao Liu 001; Ion I. Mandoiu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Supply Voltage Degradation Aware Analytical Placement. - Andrew B. Kahng; Bao Liu 001; Qinke Wang (ICCD, 2005)

Statistical gate delay calculation with crosstalk alignment consideration. - Andrew B. Kahng; Bao Liu 001; Xu Xu 001 (ACM Great Lakes Symposium on VLSI, 2006)

Efficient decoupling capacitor planning via convex programming methods. - Andrew B. Kahng; Bao Liu 001; Sheldon X.-D. Tan (ISPD, 2006)

SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching. - Andrew B. Kahng; Bao Liu 001; Sheldon X.-D. Tan (ISQED, 2006)

Constructing Current-Based Gate Models Based on Existing Timing Library. - Andrew B. Kahng; Bao Liu 001; Xu Xu 001 (ISQED, 2006)

Statistical crosstalk aggressor alignment aware interconnect delay calculation. - Andrew B. Kahng; Bao Liu 001; Xu Xu 001 (SLIP, 2006)

A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. - Bao Liu 001; Andrew B. Kahng; Xu Xu 001; Jiang Hu; Ganesh Venkataraman (ASP-DAC, 2007)

Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. - Andrew B. Kahng; Sung-Mo Kang; Wei Li; Bao Liu 001 (ICCD, 2007)

Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations. - Bao Liu 001 (ISQED, 2007)

Statistical Timing Analysis in the Presence of Signal-Integrity Effects. - Andrew B. Kahng; Bao Liu 001; Xu Xu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement. - Andrew B. Kahng; Bao Liu 001; Qinke Wang (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite and Linear Programs. - Bao Liu 001; Sheldon X.-D. Tan (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Signal Probability Based Statistical Timing Analysis. - Bao Liu 001 (DATE, 2008)

Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression. - Bao Liu 001 (DATE, 2008)

A Voltage Controlled Nano Addressing Circuit. - Bao Liu 001 (NanoNet, 2008)

Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture. - Bao Liu 001 (ASP-DAC, 2009)

Analysis and extraction of parametric variation effects on microelectrofluidics-based biochips. - Bao Liu 001 (BMAS, 2009)

Defect Mapping and Adaptive Configuration of Nanoelectronic Circuits Based on a CNT Crossbar Nano-Architecture. - Bao Liu 001 (ICCCN, 2009)

Robust differential asynchronous nanoelectronic circuits. - Bao Liu 001 (ISQED, 2009)

Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution. - Bao Liu 001 (ISQED, 2009)

Energy Efficient Swing signal generation circuits for clock distribution networks. - Khader Mohammad; Bao Liu 001; Sos S. Agaian (SMC, 2009)

Reduced Voltage Scaling in Clock Distribution Networks. - Khader Mohammad; Ayman Dodin; Bao Liu 001; Sos S. Agaian (VLSI Design, 2009)

Error-detecting/correcting-code-based self-checked/corrected/timed circuits. - Bao Liu 001 (AHS, 2010)

Voltage-controlled nano-addressing for nanosystem communication. - Bao Liu 001 (Nano Commun. Networks, 2010)

Architecture exploration of crossbar-based nanoscale reconfigurable computing platforms. - Bao Liu 001 (Nano Commun. Networks, 2010)

Statistical full-chip dynamic power estimation considering spatial correlations. - Zhigang Hao; Ruijing Shen; Sheldon X.-D. Tan; Bao Liu 001; Guoyong Shi; Yici Cai (ISQED, 2011)

Minimum logic of guaranteed single soft error resilience based on group distance-two code. - Bao Liu 001; Lu Wang (ICICDT, 2012)

Delay insensitive code-based timing and soft error-resilient and adaptive-performance logic. - Bao Liu 001; Xuemei Chen; Fiona Teshome (ISQED, 2012)

Resilient and adaptive performance logic. - Bao Liu 001; Xuemei Chen; Fiona Teshome (ACM J. Emerg. Technol. Comput. Syst., 2012)

Input-aware statistical timing analysis-based delay test pattern generation. - Bao Liu 001; Lu Wang (ISQED, 2013)

Variable latency VLSI design based on timing analysis, delay ATPG, and completion prediction. - Bao Liu 001; Lu Wang; Juan Portillo (MWSCAS, 2013)

Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks. - Bao Liu 001; Brandon Wang (DATE, 2014)

Testing, diagnosis and repair methods for NBTI-induced SRAM faults. - Bao Liu 001; Chiung-Hung Chen (ICICDT, 2014)

Input-aware statistical timing analysis for VLSI delay test and average design. - Bao Liu 001 (MWSCAS, 2014)

Power/ground supply voltage variation-aware delay test pattern generation. - Lu Wang; Xutao Wang; Milad Maleki; Bao Liu 001 (VTS, 2014)

Crosstalk-aware signal probability-based dynamic statistical timing analysis. - Yao Chen; Andrew B. Kahng; Bao Liu 001; Wenjun Wang (ISQED, 2015)

Reconfiguration-Based VLSI Design for Security. - Bao Liu 001; Brandon Wang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design. - Vivek K. De; Andrew B. Kahng; Tanay Karnik; Bao Liu 001; Milad Maleki; Lu Wang (ACM J. Emerg. Technol. Comput. Syst., 2015)

Dynamic Statistical-Timing-Analysis-Based VLSI Path Delay Test Pattern Generation. - Bao Liu 001; Lu Wang (IEEE Trans. Very Large Scale Integr. Syst., 2015)